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tkamanhug-dev
tkaman
authored and
hug-dev
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CM3DS: update SPI implementation
This commit adds the SPI driver which is now called by the SPI HAL implementation. It also removes legacy definitions. Change-Id: Iadb20dda9dfa571db3de66c3a1ce45d80d8b81b6 Signed-off-by: Tamas Kaman <[email protected]>
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10 files changed

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‎targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -53,11 +53,12 @@ typedef enum {
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} ADCName;
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typedef enum {
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SPI_0 = (int)MPS2_SSP0_BASE,
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SPI_1 = (int)MPS2_SSP1_BASE,
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SPI_2 = (int)MPS2_SSP2_BASE,
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SPI_3 = (int)MPS2_SSP3_BASE,
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SPI_4 = (int)MPS2_SSP4_BASE
56+
SPI_0 = 0,
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SPI_1,
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SPI_2,
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SPI_3,
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SPI_4,
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SPI_NC = (SPI_4 + 1)
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} SPIName;
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typedef enum {

‎targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h

Lines changed: 1 addition & 154 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
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/* MPS2 CMSIS Library
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*
3-
* Copyright (c) 2006-2017 ARM Limited
3+
* Copyright (c) 2006-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
@@ -153,154 +153,6 @@ typedef struct //
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} MPS2_SCC_TypeDef;
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155155

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/******************************************************************************/
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/* SSP Peripheral declaration */
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/******************************************************************************/
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typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
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{
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__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
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// [31:16] : Reserved
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// [15:8] : Serial clock rate
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// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
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// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
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// [5:4] : Frame format
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// [3:0] : Data Size Select
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__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
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// [31:4] : Reserved
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// [3] : Slave-mode output disable
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// [2] : Master or slave mode select
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// [1] : Synchronous serial port enable
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// [0] : Loop back mode
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__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
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// [31:16] : Reserved
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// [15:0] : Transmit/Receive FIFO
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__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
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// [31:5] : Reserved
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// [4] : PrimeCell SSP busy flag
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// [3] : Receive FIFO full
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// [2] : Receive FIFO not empty
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// [1] : Transmit FIFO not full
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// [0] : Transmit FIFO empty
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__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
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// [31:8] : Reserved
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// [8:0] : Clock prescale divisor
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__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
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// [31:4] : Reserved
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// [3] : Transmit FIFO interrupt mask
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// [2] : Receive FIFO interrupt mask
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// [1] : Receive timeout interrupt mask
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// [0] : Receive overrun interrupt mask
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__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
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// [31:4] : Reserved
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// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
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// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
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// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
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// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
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__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
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// [31:4] : Reserved
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// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
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// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
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// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
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// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
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__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
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// [31:2] : Reserved
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// [1] : Clears the SSPRTINTR interrupt
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// [0] : Clears the SSPRORINTR interrupt
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__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
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// [31:2] : Reserved
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// [1] : Transmit DMA Enable
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// [0] : Receive DMA Enable
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} MPS2_SSP_TypeDef;
215-
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// SSP_CR0 Control register 0
218-
#define SSP_CR0_DSS_Pos 0 // Data Size Select
219-
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
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#define SSP_CR0_FRF_Pos 4 // Frame Format Select
221-
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
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#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
223-
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
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#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
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#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
226-
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
227-
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
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#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
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#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
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#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
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#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
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// SSP_CR1 Control register 1
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#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
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#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
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#define SSP_CR1_SSE_Pos 1 // Serial port enable
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#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
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#define SSP_CR1_MS_Pos 2 // Master or Slave mode
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#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
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#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
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#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
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// SSP_SR Status register
245-
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
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#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
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#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
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#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
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#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
250-
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
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#define SSP_SR_RFF_Pos 3 // Receive FIFO full
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#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
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#define SSP_SR_BSY_Pos 4 // Busy
254-
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
255-
256-
// SSP_CPSR Clock prescale register
257-
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
258-
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
259-
260-
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
261-
262-
// SSPIMSC Interrupt mask set and clear register
263-
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
264-
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
265-
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
266-
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
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#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
268-
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
269-
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
270-
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
271-
272-
// SSPRIS Raw interrupt status register
273-
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
274-
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
275-
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
276-
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
277-
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
278-
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
279-
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
280-
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
281-
282-
// SSPMIS Masked interrupt status register
283-
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
284-
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
285-
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
286-
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
287-
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
288-
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
289-
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
290-
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
291-
292-
// SSPICR Interrupt clear register
293-
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
294-
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
295-
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
296-
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
297-
298-
// SSPDMACR DMA control register
299-
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
300-
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
301-
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
302-
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
303-
304156
/******************************************************************************/
305157
/* Audio and Touch Screen (I2C) Peripheral declaration */
306158
/******************************************************************************/
@@ -577,11 +429,6 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
577429
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
578430
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
579431
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
580-
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
581-
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
582-
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
583-
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
584-
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
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586433
/******************************************************************************/
587434
/* General Function Definitions */

‎targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/device_cfg.h

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -42,4 +42,12 @@
4242
/* ARM MPS2 IO SCC */
4343
#define ARM_MPS2_IO_SCC
4444

45+
/* ARM SPI PL022 */
46+
#define DEFAULT_SPI_SPEED_HZ 4000000U /* 4MHz */
47+
#define ARM_SPI0
48+
#define ARM_SPI1
49+
#define ARM_SPI2
50+
#define ARM_SPI3
51+
#define ARM_SPI4
52+
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#endif /* __ARM_LTD_DEVICE_CFG_H__ */

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