Merge pull request #2899 from TomoYamanaka/master

sg- · web-flow · commit 3aca6fdd86e7 · 2016-10-06T15:54:29.000-05:00
Fix bugs of PWM driver.
diff --git a/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_RZ_A1H/pwmout_api.c
@@ -401,8 +401,6 @@ void pwmout_period_us(pwmout_t* obj, int us) {
     if (obj->pwm >= MTU2_PWM_OFFSET) {
         /* PWM by MTU2 */
         int tmp_pwm;
-        uint16_t tmp_tgra;
-        uint16_t tmp_tgrc;
         uint8_t tmp_tcr_up;
         uint8_t tmp_tstr_sp;
         uint8_t tmp_tstr_st;
@@ -459,12 +457,10 @@ void pwmout_period_us(pwmout_t* obj, int us) {
         *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle;     // Set period
 
         // Set duty again(TGRA)
-        tmp_tgra = *TGRA_MATCH[obj->ch];
-        set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);
+        set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
         if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
             // Set duty again(TGRC)
-            tmp_tgrc = *TGRC_MATCH[obj->ch];
-            set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);
+            set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
         }
         *TMDR_MATCH[obj->ch] = 0x02;                                    // PWM mode 1
 
@@ -558,7 +554,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
                 value = (float)us / (float)period_ch1;
             }
         }
-
-        pwmout_write(obj, value);
     }
+    pwmout_write(obj, value);
 }
diff --git a/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c b/targets/TARGET_RENESAS/TARGET_VK_RZ_A1H/pwmout_api.c
@@ -542,8 +542,6 @@ void pwmout_period_us(pwmout_t* obj, int us) {
     if (pwm_mode == MODE_MTU2) {
         /* PWM by MTU2 */
         int tmp_pwm;
-        uint16_t tmp_tgra;
-        uint16_t tmp_tgrc;
         uint8_t tmp_tcr_up;
         uint8_t tmp_tstr_sp;
         uint8_t tmp_tstr_st;
@@ -600,12 +598,10 @@ void pwmout_period_us(pwmout_t* obj, int us) {
         *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle;     // Set period
 
         // Set duty again(TGRA)
-        tmp_tgra = *TGRA_MATCH[obj->ch];
-        set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);
+        set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
         if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
             // Set duty again(TGRC)
-            tmp_tgrc = *TGRC_MATCH[obj->ch];
-            set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);
+            set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
         }
         *TMDR_MATCH[obj->ch] = 0x02;                                    // PWM mode 1
 
@@ -699,7 +695,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
                 value = (float)us / (float)period_ch1;
             }
         }
-
-        pwmout_write(obj, value);
     }
+    pwmout_write(obj, value);
 }

Original file line number	Diff line number	Diff line change
`@@ -401,8 +401,6 @@ void pwmout_period_us(pwmout_t* obj, int us) {`
`401`	`401`	`if (obj->pwm >= MTU2_PWM_OFFSET) {`
`402`	`402`	`/* PWM by MTU2 */`
`403`	`403`	`int tmp_pwm;`
`404`		`- uint16_t tmp_tgra;`
`405`		`- uint16_t tmp_tgrc;`
`406`	`404`	`uint8_t tmp_tcr_up;`
`407`	`405`	`uint8_t tmp_tstr_sp;`
`408`	`406`	`uint8_t tmp_tstr_st;`
`@@ -459,12 +457,10 @@ void pwmout_period_us(pwmout_t* obj, int us) {`
`459`	`457`	`*MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period`
`460`	`458`
`461`	`459`	`// Set duty again(TGRA)`
`462`		`- tmp_tgra = *TGRA_MATCH[obj->ch];`
`463`		`- set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);`
	`460`	`+ set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);`
`464`	`461`	`if ((obj->ch == 0) \|\| (obj->ch == 3) \|\| (obj->ch == 4)) {`
`465`	`462`	`// Set duty again(TGRC)`
`466`		`- tmp_tgrc = *TGRC_MATCH[obj->ch];`
`467`		`- set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);`
	`463`	`+ set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);`
`468`	`464`	`}`
`469`	`465`	`*TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1`
`470`	`466`
`@@ -558,7 +554,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {`
`558`	`554`	`value = (float)us / (float)period_ch1;`
`559`	`555`	`}`
`560`	`556`	`}`
`561`		`-`
`562`		`- pwmout_write(obj, value);`
`563`	`557`	`}`
	`558`	`+ pwmout_write(obj, value);`
`564`	`559`	`}`
Original file line number	Diff line number	Diff line change
`@@ -542,8 +542,6 @@ void pwmout_period_us(pwmout_t* obj, int us) {`
`542`	`542`	`if (pwm_mode == MODE_MTU2) {`
`543`	`543`	`/* PWM by MTU2 */`
`544`	`544`	`int tmp_pwm;`
`545`		`- uint16_t tmp_tgra;`
`546`		`- uint16_t tmp_tgrc;`
`547`	`545`	`uint8_t tmp_tcr_up;`
`548`	`546`	`uint8_t tmp_tstr_sp;`
`549`	`547`	`uint8_t tmp_tstr_st;`
`@@ -600,12 +598,10 @@ void pwmout_period_us(pwmout_t* obj, int us) {`
`600`	`598`	`*MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period`
`601`	`599`
`602`	`600`	`// Set duty again(TGRA)`
`603`		`- tmp_tgra = *TGRA_MATCH[obj->ch];`
`604`		`- set_mtu2_duty_again(&tmp_tgra, wk_last_cycle, wk_cycle);`
	`601`	`+ set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);`
`605`	`602`	`if ((obj->ch == 0) \|\| (obj->ch == 3) \|\| (obj->ch == 4)) {`
`606`	`603`	`// Set duty again(TGRC)`
`607`		`- tmp_tgrc = *TGRC_MATCH[obj->ch];`
`608`		`- set_mtu2_duty_again(&tmp_tgrc, wk_last_cycle, wk_cycle);`
	`604`	`+ set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);`
`609`	`605`	`}`
`610`	`606`	`*TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1`
`611`	`607`
`@@ -699,7 +695,6 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {`
`699`	`695`	`value = (float)us / (float)period_ch1;`
`700`	`696`	`}`
`701`	`697`	`}`
`702`		`-`
`703`		`- pwmout_write(obj, value);`
`704`	`698`	`}`
	`699`	`+ pwmout_write(obj, value);`
`705`	`700`	`}`