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Sree Harsha Angara
committed
Updating BSP files for CYESKIT_064B0S2_4343W
1 parent e608456 commit 3b6020c

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19 files changed

+142
-221
lines changed

19 files changed

+142
-221
lines changed

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Wrapper function to initialize all generated code.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Simple wrapper header containing all generated files.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Sentinel file for determining if generated source is up to date.
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -38,9 +38,9 @@
3838

3939
void init_cycfg_clocks(void)
4040
{
41-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
42-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 255U);
43-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
41+
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
42+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 0U, 0U);
43+
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
4444
#if defined (CY_USING_HAL)
4545
cyhal_hwmgr_reserve(&CYBSP_CSD_CLK_DIV_obj);
4646
#endif //defined (CY_USING_HAL)

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Clock configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -39,7 +39,7 @@ extern "C" {
3939

4040
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
4141
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
42-
#define CYBSP_CSD_CLK_DIV_NUM 3U
42+
#define CYBSP_CSD_CLK_DIV_NUM 0U
4343

4444
#if defined (CY_USING_HAL)
4545
extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj;

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,8 +5,8 @@
55
* Contains warnings and errors that occurred while generating code for the
66
* design.
77
* This file was automatically generated and should not be modified.
8-
* cfg-backend-cli: 1.2.0.1478
9-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
8+
* Device Configurator: 2.0.0.1483
9+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
1010
*
1111
********************************************************************************
1212
* Copyright 2017-2019 Cypress Semiconductor Corporation

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -34,5 +34,5 @@ cy_stc_csd_context_t cy_csd_0_context =
3434

3535
void init_cycfg_peripherals(void)
3636
{
37-
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 3U);
37+
Cy_SysClk_PeriphAssignDivider(PCLK_CSD_CLOCK, CY_SYSCLK_DIV_8_BIT, 0U);
3838
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Peripheral Hardware Block configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -38,17 +38,17 @@ extern "C" {
3838
#define CYBSP_CSD_ENABLED 1U
3939
#define CY_CAPSENSE_CORE 4u
4040
#define CY_CAPSENSE_CPU_CLK 100000000u
41-
#define CY_CAPSENSE_PERI_CLK 100000000u
41+
#define CY_CAPSENSE_PERI_CLK 50000000u
4242
#define CY_CAPSENSE_VDDA_MV 3300u
4343
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
44-
#define CY_CAPSENSE_PERI_DIV_INDEX 3u
44+
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
4545
#define Cmod_PORT GPIO_PRT7
4646
#define CintA_PORT GPIO_PRT7
4747
#define CintB_PORT GPIO_PRT7
48-
#define Button0_Rx0_PORT GPIO_PRT8
49-
#define Button0_Tx_PORT GPIO_PRT1
50-
#define Button1_Rx0_PORT GPIO_PRT8
51-
#define Button1_Tx_PORT GPIO_PRT1
48+
#define Button0_Rx0_PORT GPIO_PRT1
49+
#define Button0_Tx_PORT GPIO_PRT8
50+
#define Button1_Rx0_PORT GPIO_PRT1
51+
#define Button1_Tx_PORT GPIO_PRT8
5252
#define LinearSlider0_Sns0_PORT GPIO_PRT8
5353
#define LinearSlider0_Sns1_PORT GPIO_PRT8
5454
#define LinearSlider0_Sns2_PORT GPIO_PRT8
@@ -57,10 +57,10 @@ extern "C" {
5757
#define Cmod_PIN 7u
5858
#define CintA_PIN 1u
5959
#define CintB_PIN 2u
60-
#define Button0_Rx0_PIN 1u
61-
#define Button0_Tx_PIN 0u
62-
#define Button1_Rx0_PIN 2u
63-
#define Button1_Tx_PIN 0u
60+
#define Button0_Rx0_PIN 0u
61+
#define Button0_Tx_PIN 1u
62+
#define Button1_Rx0_PIN 0u
63+
#define Button1_Tx_PIN 2u
6464
#define LinearSlider0_Sns0_PIN 3u
6565
#define LinearSlider0_Sns1_PIN 4u
6666
#define LinearSlider0_Sns2_PIN 5u

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -74,11 +74,11 @@ const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config =
7474
.channel_num = CYBSP_WCO_OUT_PIN,
7575
};
7676
#endif //defined (CY_USING_HAL)
77-
const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
77+
const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config =
7878
{
7979
.outVal = 1,
8080
.driveMode = CY_GPIO_DM_ANALOG,
81-
.hsiom = CYBSP_CSD_TX_HSIOM,
81+
.hsiom = CYBSP_CSD_RX_HSIOM,
8282
.intEdge = CY_GPIO_INTR_DISABLE,
8383
.intMask = 0UL,
8484
.vtrip = CY_GPIO_VTRIP_CMOS,
@@ -91,11 +91,11 @@ const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config =
9191
.vohSel = 0UL,
9292
};
9393
#if defined (CY_USING_HAL)
94-
const cyhal_resource_inst_t CYBSP_CSD_TX_obj =
94+
const cyhal_resource_inst_t CYBSP_CSD_RX_obj =
9595
{
9696
.type = CYHAL_RSC_GPIO,
97-
.block_num = CYBSP_CSD_TX_PORT_NUM,
98-
.channel_num = CYBSP_CSD_TX_PIN,
97+
.block_num = CYBSP_CSD_RX_PORT_NUM,
98+
.channel_num = CYBSP_CSD_RX_PIN,
9999
};
100100
#endif //defined (CY_USING_HAL)
101101
const cy_stc_gpio_pin_config_t CYBSP_SWO_config =
@@ -425,7 +425,7 @@ void init_cycfg_pins(void)
425425
#endif //defined (CY_USING_HAL)
426426

427427
#if defined (CY_USING_HAL)
428-
cyhal_hwmgr_reserve(&CYBSP_CSD_TX_obj);
428+
cyhal_hwmgr_reserve(&CYBSP_CSD_RX_obj);
429429
#endif //defined (CY_USING_HAL)
430430

431431
Cy_GPIO_Pin_Init(CYBSP_SWO_PORT, CYBSP_SWO_PIN, &CYBSP_SWO_config);

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CYESKIT_064B0S2_4343W/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -4,8 +4,8 @@
44
* Description:
55
* Pin configuration
66
* This file was automatically generated and should not be modified.
7-
* cfg-backend-cli: 1.2.0.1478
8-
* Device Support Library (../../../../output/psoc6/psoc6pdl): 1.4.0.1571
7+
* Device Configurator: 2.0.0.1483
8+
* Device Support Library (../../../psoc6pdl): 1.4.1.2240
99
*
1010
********************************************************************************
1111
* Copyright 2017-2019 Cypress Semiconductor Corporation
@@ -86,29 +86,29 @@ extern "C" {
8686
#if defined (CY_USING_HAL)
8787
#define CYBSP_WCO_OUT_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
8888
#endif //defined (CY_USING_HAL)
89-
#define CYBSP_CSD_TX_ENABLED 1U
90-
#define CYBSP_CSD_TX_PORT GPIO_PRT1
91-
#define CYBSP_CSD_TX_PORT_NUM 1U
92-
#define CYBSP_CSD_TX_PIN 0U
93-
#define CYBSP_CSD_TX_NUM 0U
94-
#define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG
95-
#define CYBSP_CSD_TX_INIT_DRIVESTATE 1
89+
#define CYBSP_CSD_RX_ENABLED 1U
90+
#define CYBSP_CSD_RX_PORT GPIO_PRT1
91+
#define CYBSP_CSD_RX_PORT_NUM 1U
92+
#define CYBSP_CSD_RX_PIN 0U
93+
#define CYBSP_CSD_RX_NUM 0U
94+
#define CYBSP_CSD_RX_DRIVEMODE CY_GPIO_DM_ANALOG
95+
#define CYBSP_CSD_RX_INIT_DRIVESTATE 1
9696
#ifndef ioss_0_port_1_pin_0_HSIOM
9797
#define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO
9898
#endif
99-
#define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM
100-
#define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn
99+
#define CYBSP_CSD_RX_HSIOM ioss_0_port_1_pin_0_HSIOM
100+
#define CYBSP_CSD_RX_IRQ ioss_interrupts_gpio_1_IRQn
101101
#if defined (CY_USING_HAL)
102-
#define CYBSP_CSD_TX_HAL_PORT_PIN P1_0
102+
#define CYBSP_CSD_RX_HAL_PORT_PIN P1_0
103103
#endif //defined (CY_USING_HAL)
104104
#if defined (CY_USING_HAL)
105-
#define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
105+
#define CYBSP_CSD_RX_HAL_IRQ CYHAL_GPIO_IRQ_NONE
106106
#endif //defined (CY_USING_HAL)
107107
#if defined (CY_USING_HAL)
108-
#define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT
108+
#define CYBSP_CSD_RX_HAL_DIR CYHAL_GPIO_DIR_INPUT
109109
#endif //defined (CY_USING_HAL)
110110
#if defined (CY_USING_HAL)
111-
#define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
111+
#define CYBSP_CSD_RX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG
112112
#endif //defined (CY_USING_HAL)
113113
#define CYBSP_SWO_ENABLED 1U
114114
#define CYBSP_SWO_PORT GPIO_PRT6
@@ -431,9 +431,9 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config;
431431
#if defined (CY_USING_HAL)
432432
extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj;
433433
#endif //defined (CY_USING_HAL)
434-
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config;
434+
extern const cy_stc_gpio_pin_config_t CYBSP_CSD_RX_config;
435435
#if defined (CY_USING_HAL)
436-
extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj;
436+
extern const cyhal_resource_inst_t CYBSP_CSD_RX_obj;
437437
#endif //defined (CY_USING_HAL)
438438
extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config;
439439
#if defined (CY_USING_HAL)

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