Skip to content

Commit 40627a5

Browse files
gaborkerteszOren Cohen
gaborkertesz
authored and
Oren Cohen
committed
Fix last issues
Imports working McuBoot for reset. Updates microsec ticker driver. Default baudrate is set to 115200 to see TF-M boot messages. Stack top is set to scatter file dependent and not hard-coded.
1 parent bde2557 commit 40627a5

File tree

6 files changed

+143
-114
lines changed

6 files changed

+143
-114
lines changed

‎platform/mbed_lib.json

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,12 @@
130130
}
131131
},
132132
"target_overrides": {
133+
"ARM_MUSCA_A1_NS": {
134+
"stdio-baud-rate": 115200
135+
},
136+
"ARM_MUSCA_A1_S": {
137+
"stdio-baud-rate": 115200
138+
},
133139
"EFM32": {
134140
"stdio-baud-rate": 115200
135141
},

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/device/TOOLCHAIN_ARMC6/startup_cmsdk_musca_ns.S

Lines changed: 95 additions & 95 deletions
Original file line numberDiff line numberDiff line change
@@ -23,111 +23,111 @@
2323
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
2424
;*/
2525

26-
__initial_sp EQU 0x20020000 ; Top of RAM
27-
2826
; Vector Table Mapped to Address 0 at Reset
2927

3028
AREA VECTOR, DATA, READONLY
3129
EXPORT __Vectors
3230
EXPORT __Vectors_End
3331
EXPORT __Vectors_Size
3432

33+
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
34+
3535
__Vectors ;Core Interrupts
36-
DCD __initial_sp ; Top of Stack
37-
DCD Reset_Handler ; Reset Handler
38-
DCD NMI_Handler ; NMI Handler
39-
DCD HardFault_Handler ; Hard Fault Handler
40-
DCD MemManage_Handler ; MPU Fault Handler
41-
DCD BusFault_Handler ; Bus Fault Handler
42-
DCD UsageFault_Handler ; Usage Fault Handler
43-
DCD 0 ; Reserved
44-
DCD 0 ; Reserved
45-
DCD 0 ; Reserved
46-
DCD 0 ; Reserved
47-
DCD SVC_Handler ; SVCall Handler
48-
DCD DebugMon_Handler ; Debug Monitor Handler
49-
DCD 0 ; Reserved
50-
DCD PendSV_Handler ; PendSV Handler
51-
DCD SysTick_Handler ; SysTick Handler
36+
DCD |Image$$ARM_LIB_STACK$$ZI$$Limit|; Top of Stack
37+
DCD Reset_Handler ; Reset Handler
38+
DCD NMI_Handler ; NMI Handler
39+
DCD HardFault_Handler ; Hard Fault Handler
40+
DCD MemManage_Handler ; MPU Fault Handler
41+
DCD BusFault_Handler ; Bus Fault Handler
42+
DCD UsageFault_Handler ; Usage Fault Handler
43+
DCD 0 ; Reserved
44+
DCD 0 ; Reserved
45+
DCD 0 ; Reserved
46+
DCD 0 ; Reserved
47+
DCD SVC_Handler ; SVCall Handler
48+
DCD DebugMon_Handler ; Debug Monitor Handler
49+
DCD 0 ; Reserved
50+
DCD PendSV_Handler ; PendSV Handler
51+
DCD SysTick_Handler ; SysTick Handler
5252
;SSE-200 Interrupts
53-
DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
54-
DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
55-
DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
56-
DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
57-
DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
58-
DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
59-
DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
60-
DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
61-
DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
62-
DCD 0 ; 9: Reserved
63-
DCD 0 ; 10: Reserved
64-
DCD 0 ; 11: Reserved
65-
DCD 0 ; 12: Reserved
66-
DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
67-
DCD 0 ; 14: Reserved
68-
DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
69-
DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
70-
DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
71-
DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
72-
DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
73-
DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
74-
DCD 0 ; 21: Reserved
75-
DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
76-
DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
77-
DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
78-
DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
79-
DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
80-
DCD 0 ; 27: Reserved
81-
DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
82-
DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
83-
DCD 0 ; 30: Reserved
84-
DCD 0 ; 31: Reserved
53+
DCD NS_WATCHDOG_RESET_IRQHandler ; 0: Non-Secure Watchdog Reset Request Interrupt
54+
DCD NS_WATCHDOG_IRQHandler ; 1: Non-Secure Watchdog Interrupt
55+
DCD S32K_TIMER_IRQHandler ; 2: S32K Timer Interrupt
56+
DCD TIMER0_IRQHandler ; 3: CMSDK Timer 0 Interrupt
57+
DCD TIMER1_IRQHandler ; 4: CMSDK Timer 1 Interrupt
58+
DCD DUALTIMER_IRQHandler ; 5: CMSDK Dual Timer Interrupt
59+
DCD MHU0_IRQHandler ; 6: Message Handling Unit 0 Interrupt
60+
DCD MHU1_IRQHandler ; 7: Message Handling Unit 1 Interrupt
61+
DCD CRYPTOCELL_IRQHandler ; 8: CryptoCell-312 Interrupt
62+
DCD 0 ; 9: Reserved
63+
DCD 0 ; 10: Reserved
64+
DCD 0 ; 11: Reserved
65+
DCD 0 ; 12: Reserved
66+
DCD I_CACHE_INV_ERR_IRQHandler ; 13: Intsruction Cache Invalidation Interrupt
67+
DCD 0 ; 14: Reserved
68+
DCD SYS_PPU_IRQHandler ; 15: System PPU Interrupt
69+
DCD CPU0_PPU_IRQHandler ; 16: CPU0 PPU Interrupt
70+
DCD CPU1_PPU_IRQHandler ; 17: CPU1 PPU Interrupt
71+
DCD CPU0_DGB_PPU_IRQHandler ; 18: CPU0 Debug PPU Interrupt
72+
DCD CPU1_DGB_PPU_IRQHandler ; 19: CPU1 Debug PPU Interrupt
73+
DCD CRYPTOCELL_PPU_IRQHandler ; 20: CryptoCell PPU Interrupt
74+
DCD 0 ; 21: Reserved
75+
DCD RAM0_PPU_IRQHandler ; 22: RAM 0 PPU Interrupt
76+
DCD RAM1_PPU_IRQHandler ; 23: RAM 1 PPU Interrupt
77+
DCD RAM2_PPU_IRQHandler ; 24: RAM 2 PPU Interrupt
78+
DCD RAM3_PPU_IRQHandler ; 25: RAM 3 PPU Interrupt
79+
DCD DEBUG_PPU_IRQHandler ; 26: Debug PPU Interrupt
80+
DCD 0 ; 27: Reserved
81+
DCD CPU0_CTI_IRQHandler ; 28: CPU0 CTI Interrupt
82+
DCD CPU1_CTI_IRQHandler ; 29: CPU1 CTI Interrupt
83+
DCD 0 ; 30: Reserved
84+
DCD 0 ; 31: Reserved
8585
;Expansion Interrupts
86-
DCD 0 ; 32: Reserved
87-
DCD GpTimer_IRQHandler ; 33: General Purpose Timer
88-
DCD I2C0_IRQHandler ; 34: I2C0
89-
DCD I2C1_IRQHandler ; 35: I2C1
90-
DCD I2S_IRQHandler ; 36: I2S
91-
DCD SPI_IRQHandler ; 37: SPI
92-
DCD QSPI_IRQHandler ; 38: QSPI
93-
DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
94-
DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
95-
DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
96-
DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
97-
DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
98-
DCD UART0_IRQHandler ; 44: UART0 interrupt
99-
DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
100-
DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
101-
DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
102-
DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
103-
DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
104-
DCD UART1_IRQHandler ; 50: UART0 interrupt
105-
DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
106-
DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
107-
DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
108-
DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
109-
DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
110-
DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
111-
DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
112-
DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
113-
DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
114-
DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
115-
DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
116-
DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
117-
DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
118-
DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
119-
DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
120-
DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
121-
DCD Combined_IRQHandler ; 67: Combined interrupt
122-
DCD PVT_IRQHandler ; 68: PVT sensor interrupt
123-
DCD 0 ; 69: Reserved
124-
DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
125-
DCD RTC_IRQHandler ; 71: RTC interrupt
126-
DCD GpTimer1_IRQHandler ; 72: General Purpose Timer1
127-
DCD GpTimer0_IRQHandler ; 73: General Purpose Timer0
128-
DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
129-
DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
130-
DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
86+
DCD 0 ; 32: Reserved
87+
DCD GpTimer_IRQHandler ; 33: General Purpose Timer
88+
DCD I2C0_IRQHandler ; 34: I2C0
89+
DCD I2C1_IRQHandler ; 35: I2C1
90+
DCD I2S_IRQHandler ; 36: I2S
91+
DCD SPI_IRQHandler ; 37: SPI
92+
DCD QSPI_IRQHandler ; 38: QSPI
93+
DCD UARTRX0_Handler ; 39: UART0 receive FIFO interrupt
94+
DCD UARTTX0_Handler ; 40: UART0 transmit FIFO interrupt
95+
DCD UART0_RxTimeout_IRQHandler ; 41: UART0 receive timeout interrupt
96+
DCD UART0_ModemStatus_IRQHandler ; 42: UART0 modem status interrupt
97+
DCD UART0_Error_IRQHandler ; 43: UART0 error interrupt
98+
DCD UART0_IRQHandler ; 44: UART0 interrupt
99+
DCD UARTRX1_Handler ; 45: UART0 receive FIFO interrupt
100+
DCD UARTTX1_Handler ; 46: UART0 transmit FIFO interrupt
101+
DCD UART1_RxTimeout_IRQHandler ; 47: UART0 receive timeout interrupt
102+
DCD UART1_ModemStatus_IRQHandler ; 48: UART0 modem status interrupt
103+
DCD UART1_Error_IRQHandler ; 49: UART0 error interrupt
104+
DCD UART1_IRQHandler ; 50: UART0 interrupt
105+
DCD GPIO_0_IRQHandler ; 51: GPIO 0 interrupt
106+
DCD GPIO_1_IRQHandler ; 52: GPIO 1 interrupt
107+
DCD GPIO_2_IRQHandler ; 53: GPIO 2 interrupt
108+
DCD GPIO_3_IRQHandler ; 54: GPIO 3 interrupt
109+
DCD GPIO_4_IRQHandler ; 55: GPIO 4 interrupt
110+
DCD GPIO_5_IRQHandler ; 56: GPIO 5 interrupt
111+
DCD GPIO_6_IRQHandler ; 57: GPIO 6 interrupt
112+
DCD GPIO_7_IRQHandler ; 58: GPIO 7 interrupt
113+
DCD GPIO_8_IRQHandler ; 59: GPIO 8 interrupt
114+
DCD GPIO_9_IRQHandler ; 60: GPIO 9 interrupt
115+
DCD GPIO_10_IRQHandler ; 61: GPIO 10 interrupt
116+
DCD GPIO_11_IRQHandler ; 62: GPIO 11 interrupt
117+
DCD GPIO_12_IRQHandler ; 63: GPIO 12 interrupt
118+
DCD GPIO_13_IRQHandler ; 64: GPIO 13 interrupt
119+
DCD GPIO_14_IRQHandler ; 65: GPIO 14 interrupt
120+
DCD GPIO_15_IRQHandler ; 66: GPIO 15 interrupt
121+
DCD Combined_IRQHandler ; 67: Combined interrupt
122+
DCD PVT_IRQHandler ; 68: PVT sensor interrupt
123+
DCD 0 ; 69: Reserved
124+
DCD PWM_0_IRQHandler ; 70: PWM0 interrupt
125+
DCD RTC_IRQHandler ; 71: RTC interrupt
126+
DCD GpTimer1_IRQHandler ; 72: General Purpose Timer1
127+
DCD GpTimer0_IRQHandler ; 73: General Purpose Timer0
128+
DCD PWM_1_IRQHandler ; 74: PWM1 interrupt
129+
DCD PWM_2_IRQHandler ; 75: PWM2 interrupt
130+
DCD IOMUX_IRQHandler ; 76: IOMUX interrupt
131131

132132
__Vectors_End
133133

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/README.md

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,16 @@ Built by mbed-cli using GNU Arm Embedded - version 6.3.1
66

77
These images were compiled by the following command:
88

9+
## mcuboot.bin
10+
### Repository
11+
https://git.trustedfirmware.org/trusted-firmware-m.git
12+
### Commit SHA
13+
8da7f102a6a6a1a99462f7f32edbd1565096c2f3
14+
```sh
15+
cmake ../ -G"Unix Makefiles" -DTARGET_PLATFORM=MUSCA_A -DCOMPILER=ARMCLANG -DCMAKE_BUILD_TYPE=Debug
16+
make
17+
```
18+
919
## tfm.bin
1020

1121
```sh

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/prebuilt/mcuboot.bin

5.05 KB
Binary file not shown.

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/TARGET_MUSCA_A1_NS/us_ticker.c

Lines changed: 28 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/* mbed Microcontroller Library
2-
* Copyright (c) 2019 Arm Limited
2+
* Copyright (c) 2017-2019 Arm Limited
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -22,10 +22,15 @@
2222
*/
2323

2424
#include "device.h"
25+
#include "mbed_critical.h"
2526
#include "timer_cmsdk_drv.h"
2627
#include "us_ticker_api.h"
2728

2829
static uint64_t total_ticks = 0;
30+
/* Stores the last reload value, or the last tick value read when a read API
31+
* call occurs from the upper layer, needed to keep total_ticks
32+
* accumulated properly.
33+
*/
2934
static uint32_t previous_ticks = 0;
3035

3136
static void restart_timer(uint32_t new_reload)
@@ -39,6 +44,23 @@ static void restart_timer(uint32_t new_reload)
3944
timer_cmsdk_enable(&USEC_TIMER_DEV);
4045
}
4146

47+
static void update_ticker(void)
48+
{
49+
if (timer_cmsdk_is_interrupt_active(&USEC_TIMER_DEV)) {
50+
total_ticks += previous_ticks;
51+
previous_ticks = TIMER_CMSDK_MAX_RELOAD;
52+
restart_timer(previous_ticks);
53+
} else {
54+
uint32_t tick = timer_cmsdk_get_current_value(&USEC_TIMER_DEV);
55+
56+
if (tick < previous_ticks) {
57+
uint32_t delta = previous_ticks - tick;
58+
total_ticks += delta;
59+
previous_ticks = tick;
60+
}
61+
}
62+
}
63+
4264
void us_ticker_init(void)
4365
{
4466
timer_cmsdk_init(&USEC_TIMER_DEV);
@@ -54,20 +76,11 @@ void us_ticker_free(void)
5476

5577
uint32_t us_ticker_read(void)
5678
{
57-
if (timer_cmsdk_is_interrupt_active(&USEC_TIMER_DEV)) {
58-
total_ticks += previous_ticks;
59-
previous_ticks = TIMER_CMSDK_MAX_RELOAD;
60-
restart_timer(previous_ticks);
61-
}
62-
uint32_t tick = timer_cmsdk_get_current_value(&USEC_TIMER_DEV);
63-
64-
if (tick < previous_ticks) {
65-
uint32_t delta = previous_ticks - tick;
66-
total_ticks += delta;
67-
previous_ticks = tick;
68-
}
79+
core_util_critical_section_enter();
80+
update_ticker();
81+
core_util_critical_section_exit();
6982

70-
return (total_ticks >> USEC_REPORTED_SHIFT);
83+
return (uint32_t)(total_ticks >> USEC_REPORTED_SHIFT);
7184
}
7285

7386
void us_ticker_set_interrupt(timestamp_t timestamp)
@@ -106,6 +119,6 @@ const ticker_info_t* us_ticker_get_info()
106119
#endif
107120
void usec_interval_irq_handler(void)
108121
{
109-
us_ticker_read();
122+
update_ticker();
110123
us_ticker_irq_handler();
111124
}

‎targets/TARGET_ARM_SSG/TARGET_MUSCA_A1/device/system_cmsdk_musca.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* Copyright (c) 2017-2019 ARM Limited
2+
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*
@@ -14,10 +14,10 @@
1414
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
1515
* See the License for the specific language governing permissions and
1616
* limitations under the License.
17-
*/
18-
19-
/*
17+
*
2018
* This file is derivative of CMSIS V5.01 \Device\ARM\ARMCM33\Source\system_ARMCM33.c
19+
* https://github.com/ARM-software/CMSIS_5/tree/5.0.1
20+
* Git SHA: 8a1d9d6ee18b143ae5befefa14d89fb5b3f99c75
2121
*/
2222

2323
#include "system_cmsdk_musca.h"

0 commit comments

Comments
 (0)