Merge pull request #11366 from 0xc0170/dev_rollup

Rollup part 2 for 5.14

Author: 0xc0170

TESTS/mbed_hal/qspi/flash_configs/MX25LM51245G_config.h

@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2018-2018 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_QSPI_FLASH_MX25LM51245G_H
+#define MBED_QSPI_FLASH_MX25LM51245G_H
+
+
+#define QSPI_FLASH_CHIP_STRING "macronix MX25LM51245G"
+
+// Command for reading status register
+#define QSPI_CMD_RDSR                           0x05
+// Command for reading configuration register
+#define QSPI_CMD_RDCR0                          0x15
+#define QSPI_CMD_RDCR1                          0x71
+// Command for writing status/configuration register
+#define QSPI_CMD_WRSR                           0x01
+// Command for reading security register
+#define QSPI_CMD_RDSCUR                         0x2B
+
+// Command for setting Reset Enable
+#define QSPI_CMD_RSTEN                          0x66
+// Command for setting Reset
+#define QSPI_CMD_RST                            0x99
+
+// Command for setting write enable
+#define QSPI_CMD_WREN                           0x06
+// Command for setting write disable
+#define QSPI_CMD_WRDI                           0x04
+
+// WRSR operations max time [us] (datasheet max time + 15%)
+#define QSPI_WRSR_MAX_TIME                      34500   // 30ms
+// general wait max time [us]
+#define QSPI_WAIT_MAX_TIME                      100000  // 100ms
+
+
+// Commands for writing (page programming)
+// Only single/octal mode supported with this memory
+// So only single 1-1-1 mode in this QSPI config
+#define QSPI_CMD_WRITE_1IO                      0x02    // 1-1-1 mode
+// write operations max time [us] (datasheet max time + 15%)
+#define QSPI_PAGE_PROG_MAX_TIME                 11500   // 10ms
+
+#define QSPI_PAGE_SIZE                          256     // 256B
+#define QSPI_SECTOR_SIZE                        4096    // 4kB
+#define QSPI_SECTOR_COUNT                       2048
+
+// Commands for reading
+// Only single/octal mode supported with this memory
+// So only single 1-1-1 mode in this QSPI config
+#define QSPI_CMD_READ_1IO_FAST                  0x0B   // 1-1-1 mode
+#define QSPI_CMD_READ_1IO                       0x03   // 1-1-1 mode
+
+#define QSPI_READ_1IO_DUMMY_CYCLE               0
+#define QSPI_READ_FAST_DUMMY_CYCLE              8
+
+// Commands for erasing
+#define QSPI_CMD_ERASE_SECTOR                   0x20    // 4kB
+//#define QSPI_CMD_ERASE_BLOCK_32   // not supported, only ersae block 64
+#define QSPI_CMD_ERASE_BLOCK_64                 0xD8    // 64kB
+#define QSPI_CMD_ERASE_CHIP                     0x60    // or 0xC7
+
+// erase operations max time [us] (datasheet max time + 15%)
+#define QSPI_ERASE_SECTOR_MAX_TIME              480000      // 400 ms
+#define QSPI_ERASE_BLOCK_64_MAX_TIME            2400000     // 2s
+
+// max frequency for basic rw operation (for fast mode)
+#define QSPI_COMMON_MAX_FREQUENCY               1000000
+
+#define QSPI_STATUS_REG_SIZE                    1 //2 ??
+#define QSPI_CONFIG_REG_0_SIZE                  1
+#define QSPI_CONFIG_REG_1_SIZE                  1
+#define QSPI_SECURITY_REG_SIZE                  1
+#define QSPI_MAX_REG_SIZE                       2
+
+// status register
+#define STATUS_BIT_WIP   (1 << 0)   // write in progress bit
+#define STATUS_BIT_WEL   (1 << 1)   // write enable latch
+#define STATUS_BIT_BP0   (1 << 2)   //
+#define STATUS_BIT_BP1   (1 << 3)   //
+#define STATUS_BIT_BP2   (1 << 4)   //
+#define STATUS_BIT_BP3   (1 << 5)   //
+//#define STATUS_BIT_QE    (1 << 6)   // Not supported
+//#define STATUS_BIT_SRWD  (1 << 7)   // Not supported
+
+// configuration register 0
+// bit 0, 1, 2, 4, 5, 7 reserved
+#define CONFIG0_BIT_TB   (1 << 3)   // Top/Bottom area protect
+
+#endif // MBED_QSPI_FLASH_MX25LM51245G_H

TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

@@ -32,6 +32,9 @@
 #elif defined(TARGET_DISCO_F769NI)
 #include "MX25L51245G_config.h" // MX25L51245G
 
+#elif defined(TARGET_DISCO_L4R9I)
+#include "MX25LM51245G_config.h" // MX25LM51245G
+
 #elif defined(TARGET_DISCO_L476VG)
 #include "N25Q128A_config.h" // N25Q128A13EF840E
 /* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */

TESTS/mbed_hal/qspi/main.cpp

@@ -77,10 +77,19 @@ struct Qspi {
 
 
 #define READ_1_1_1      MODE_1_1_1, QSPI_CMD_READ_1IO,  QSPI_READ_1IO_DUMMY_CYCLE
+#ifdef QSPI_CMD_READ_1I2O
 #define READ_1_1_2      MODE_1_1_2, QSPI_CMD_READ_1I2O, QSPI_READ_1I2O_DUMMY_CYCLE
+#endif
+#ifdef QSPI_CMD_READ_2IO
 #define READ_1_2_2      MODE_1_2_2, QSPI_CMD_READ_2IO,  QSPI_READ_2IO_DUMMY_CYCLE
+#endif
+#ifdef QSPI_CMD_READ_1I4O
 #define READ_1_1_4      MODE_1_1_4, QSPI_CMD_READ_1I4O, QSPI_READ_1I4O_DUMMY_CYCLE
+#endif
+#ifdef QSPI_CMD_READ_4IO
 #define READ_1_4_4      MODE_1_4_4, QSPI_CMD_READ_4IO,  QSPI_READ_4IO_DUMMY_CYCLE
+#endif
+
 #ifdef QSPI_CMD_READ_DPI
 #define READ_2_2_2      MODE_2_2_2, QSPI_CMD_READ_DPI,  QSPI_READ_2IO_DUMMY_CYCLE
 #endif

TESTS/mbed_hal/qspi/qspi_test_utils.h

@@ -722,7 +722,19 @@ int32_t ATHandler::read_int()
         return -1;
     }
 
-    return std::strtol(buff, NULL, 10);
+    errno = 0;
+    char *endptr;
+    long result = std::strtol(buff, &endptr, 10);
+    if ((result == LONG_MIN || result == LONG_MAX) && errno == ERANGE) {
+        return -1; // overflow/underflow
+    }
+    if (result < 0) {
+        return -1; // negative values are unsupported
+    }
+    if (*buff == '\0') {
+        return -1; // empty string
+    }
+    return (int32_t) result;
 }
 
 void ATHandler::set_delimiter(char delimiter)

features/cellular/framework/AT/ATHandler.cpp

@@ -416,9 +416,9 @@ class ATHandler {
      */
     ssize_t read_hex_string(char *str, size_t size);
 
-    /** Reads as string and converts result to integer. Supports only positive integers.
+    /** Reads as string and converts result to integer. Supports only non-negative integers.
      *
-     *  @return the positive integer or -1 in case of error.
+     *  @return the non-negative integer or -1 in case of error.
      */
     int32_t read_int();
 

features/cellular/framework/AT/ATHandler.h

@@ -1414,7 +1414,7 @@ int TDBStore::do_reserved_data_get(void *reserved_data, size_t reserved_data_buf
 
     while (actual_size) {
         uint32_t chunk = std::min(work_buf_size, (uint32_t) actual_size);
-        ret = read_area(_active_area, offset, chunk, buf);
+        ret = read_area(_active_area, offset, chunk, buf + offset);
         if (ret) {
             return ret;
         }

features/storage/kvstore/tdbstore/TDBStore.cpp

@@ -97,6 +97,7 @@ bool Mutex::trylock_for(uint32_t millisec)
 {
     osStatus status = osMutexAcquire(_id, millisec);
     if (status == osOK) {
+        _count++;
         return true;
     }
 

rtos/source/Mutex.cpp

@@ -2592,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2658,7 +2658,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */

targets/TARGET_STM/TARGET_STM32F0/device/stm32f0xx_hal_i2c.c

@@ -2592,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
+    hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2666,7 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
+    hi2c->XferOptions = XferOptions;
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */