Workaround(recommended by compiler team) for FVP_MPS2 targets to use ARM Compiler 6

SenRamakri · SenRamakri · commit 45c727ee6fb4 · 2019-03-01T13:40:42.000-06:00
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -53,11 +53,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M0P/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M3/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M4/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }
diff --git a/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct b/targets/TARGET_ARM_FM/TARGET_FVP_MPS2/TARGET_FVP_MPS2_M7/device/TOOLCHAIN_ARM_STD/MPS2.sct
@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE  {
 LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {    ; load region size_region
   ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE  {  ; load address = execution address
    *(InRoot$$Sections)
-   .ANY (+RO)
+   *(+RO)
   }
   ; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM
   RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE)  {  ; RW data
-   .ANY (+RW +ZI)
+   *(+RW +ZI)
   }
   ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down
   }
diff --git a/targets/targets.json b/targets/targets.json
@@ -7654,7 +7654,7 @@
     "FVP_MPS2": {
         "inherits": ["ARM_FM"],
         "public": false,
-        "supported_toolchains": ["GCC_ARM", "ARMC5", "IAR"],
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
         "OUTPUT_EXT": "elf",
         "device_has": [
             "AACI",

Original file line number	Diff line number	Diff line change
`@@ -53,11 +53,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {`
`53`	`53`	`LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region`
`54`	`54`	`ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address`
`55`	`55`	`*(InRoot$$Sections)`
`56`		`- .ANY (+RO)`
	`56`	`+ *(+RO)`
`57`	`57`	`}`
`58`	`58`	`; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM`
`59`	`59`	`RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE) { ; RW data`
`60`		`- .ANY (+RW +ZI)`
	`60`	`+ *(+RW +ZI)`
`61`	`61`	`}`
`62`	`62`	`ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down`
`63`	`63`	`}`
Original file line number	Diff line number	Diff line change
`@@ -57,11 +57,11 @@ LR_IROM1 MAPPABLE_START MAPPABLE_SIZE {`
`57`	`57`	`LR_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load region size_region`
`58`	`58`	`ER_IROM2 ZBT_SRAM1_START ZBT_SRAM1_SIZE { ; load address = execution address`
`59`	`59`	`*(InRoot$$Sections)`
`60`		`- .ANY (+RO)`
	`60`	`+ *(+RO)`
`61`	`61`	`}`
`62`	`62`	`; NVIC_VECTORS_SIZE Total: 64 vectors = 256 bytes (0x100) to be reserved in RAM`
`63`	`63`	`RW_IRAM1 (ZBT_SRAM2_START + NVIC_VECTORS_SIZE) (ZBT_SRAM2_SIZE - NVIC_VECTORS_SIZE - STACK_SIZE) { ; RW data`
`64`		`- .ANY (+RW +ZI)`
	`64`	`+ *(+RW +ZI)`
`65`	`65`	`}`
`66`	`66`	`ARM_LIB_STACK (ZBT_SRAM2_START + ZBT_SRAM2_SIZE) EMPTY - STACK_SIZE { ; Stack region growing down`
`67`	`67`	`}`