PSOC6: use prebuilt CM0+ C arrays instead of HEX images

Replace the prebuilt CM0+ HEX images with C files that provide the
variable cy_m0p_image placed to the combined ELF image with linker
script. This simplifies build flow of PSoC 6 application and improves
compatibility with IDE export targets. It is still possible to use
the custom prebuilt HEX images for PSA targets that remove CM0P_SLEEP
label and specify the `hex_filename` in targets.json.
Linker scripts are compatible with both scenarios.

Author: vmedcy

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/device/TOOLCHAIN_ARM/cy8c6xxa_cm4_dual.sct

@@ -43,7 +43,7 @@
 ;******************************************************************************/
 
 #if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10002000
+  #define MBED_ROM_START    0x10000000
 #endif
 
 ;* MBED_APP_START is being  used by the bootloader build script and
@@ -55,7 +55,7 @@
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x001FE000
+  #define MBED_ROM_SIZE     0x00200000
 #endif
 
 ;* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -133,8 +133,26 @@
 #define EFUSE_START             0x90700000
 #define EFUSE_SIZE              0x100000
 
+; Size and start address of the Cortex-M0+ application image
+#define FLASH_CM0P_SIZE         0x2000
+#define FLASH_CM0P_START        FLASH_START
 
-LR_IROM1 FLASH_START FLASH_SIZE
+; Size and start address of the Cortex-M4 application image
+#define FLASH_CM4_SIZE          (FLASH_SIZE - FLASH_CM0P_SIZE)
+#define FLASH_CM4_START         (FLASH_CM0P_START + FLASH_CM0P_SIZE)
+
+
+; Cortex-M0+ application image
+LR_IROM FLASH_CM0P_START FLASH_CM0P_SIZE
+{
+    .cy_m0p_image +0 FLASH_CM0P_SIZE
+    {
+        * (.cy_m0p_image)
+    }
+}
+
+; Cortex-M4 application image
+LR_IROM1 FLASH_CM4_START FLASH_CM4_SIZE
 {
     ER_FLASH_VECTORS +0
     {

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/device/TOOLCHAIN_GCC_ARM/cy8c6xxa_cm4_dual.ld

@@ -41,7 +41,7 @@ GROUP(-lgcc -lc -lnosys)
 ENTRY(Reset_Handler)
 
 #if !defined(MBED_ROM_START)
-  #define MBED_ROM_START    0x10002000
+  #define MBED_ROM_START    0x10000000
 #endif
 
 /* MBED_APP_START is being  used by the bootloader build script and
@@ -53,7 +53,7 @@ ENTRY(Reset_Handler)
 #endif
 
 #if !defined(MBED_ROM_SIZE)
-  #define MBED_ROM_SIZE     0x001FE000
+  #define MBED_ROM_SIZE     0x00200000
 #endif
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -118,6 +118,13 @@ MEMORY
     efuse             (r)     : ORIGIN = 0x90700000, LENGTH = 0x100000     /*   1 MB */
 }
 
+/* Size and start address of the Cortex-M0+ application image */
+FLASH_CM0P_SIZE  = 0x2000;
+FLASH_CM0P_START = ORIGIN(flash);
+/* Size and start address of the Cortex-M4 application image */
+FLASH_CM4_SIZE   = LENGTH(flash) - FLASH_CM0P_SIZE;
+FLASH_CM4_START  = FLASH_CM0P_START + FLASH_CM0P_SIZE;
+
 /* Library configurations */
 GROUP(libgcc.a libc.a libm.a libnosys.a)
 
@@ -157,7 +164,17 @@ GROUP(libgcc.a libc.a libm.a libnosys.a)
 
 SECTIONS
 {
-    .text :
+     /* Cortex-M0+ application image */
+    .cy_m0p_image FLASH_CM0P_START :
+    {
+        . = ALIGN(4);
+        __cy_m0p_code_start = . ;
+        KEEP(*(.cy_m0p_image))
+        __cy_m0p_code_end = . ;
+    } > flash
+
+    /* Cortex-M4 application image */
+    .text FLASH_CM4_START :
     {
         . = ALIGN(4);
         __Vectors = . ;

targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_4343W/device/TOOLCHAIN_IAR/cy8c6xxa_cm4_dual.icf

@@ -42,7 +42,7 @@
 define symbol __ICFEDIT_intvec_start__ = 0x00000000;
 
 if (!isdefinedsymbol(MBED_ROM_START)) {
-  define symbol MBED_ROM_START = 0x10002000;
+  define symbol MBED_ROM_START = 0x10000000;
 }
 
 /* MBED_APP_START is being  used by the bootloader build script and
@@ -54,7 +54,7 @@ if (!isdefinedsymbol(MBED_APP_START)) {
 }
 
 if (!isdefinedsymbol(MBED_ROM_SIZE)) {
-  define symbol MBED_ROM_SIZE = 0x001FE000;
+  define symbol MBED_ROM_SIZE = 0x00200000;
 }
 
 /* MBED_APP_SIZE is being  used by the bootloader build script and
@@ -161,6 +161,9 @@ if (!isdefinedsymbol(__HEAP_SIZE)) {
 }
 /**** End of ICF editor section. ###ICF###*/
 
+/* Size of the Cortex-M0+ application image */
+define symbol FLASH_CM0P_SIZE  = 0x2000;
+
 define memory mem with size = 4G;
 define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
 define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
@@ -182,6 +185,7 @@ define block RAM with fixed order {block RAM_DATA, block RAM_OTHER, block RAM_NO
 define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__ { };
 define block HEAP       with alignment = 8, size = __ICFEDIT_size_heap__ { };
 
+define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
 define block RO     {first section .intvec, readonly};
 
 /*-Initializations-*/
@@ -190,8 +194,11 @@ do not initialize  { section .noinit, section .intvec_ram };
 
 /*-Placement-*/
 
-/* Flash */
-place at start of IROM1_region  { block RO };
+/* Flash - Cortex-M0+ application image */
+place at start of IROM1_region  { block CM0P_RO };
+
+/* Flash - Cortex-M4 application image */
+place in          IROM1_region  { block RO };
 ".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
 
 /* Emulated EEPROM Flash area */
@@ -228,7 +235,8 @@ place at end   of IRAM1_region  { block CSTACK };
 ".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
 
 
-keep {  section .cy_app_signature,
+keep {  section .cy_m0p_image,
+        section .cy_app_signature,
         section .cy_em_eeprom,
         section .cy_sflash_user_data,
         section .cy_sflash_nar,