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jeromecoutantjeromecoutant
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NUCLEO_WB55RG: enable USBDEVICE
1 parent 26223e6 commit 551f8b4

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4 files changed

+63
-5
lines changed

4 files changed

+63
-5
lines changed

‎targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,7 @@
2525
* AHBCLK (MHz) | 32
2626
* APB1CLK (MHz) | 32
2727
* APB2CLK (MHz) | 32
28-
* USB capable | NO // todo
28+
* USB capable | YES
2929
*-----------------------------------------------------------------------------
3030
**/
3131

@@ -97,13 +97,14 @@ void SetSysClock(void)
9797
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
9898
RCC_ClkInitStruct.AHBCLK2Divider = RCC_SYSCLK_DIV1;
9999
RCC_ClkInitStruct.AHBCLK4Divider = RCC_SYSCLK_DIV1;
100-
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK) {
100+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
101101
error("HAL_RCC_ClockConfig error\n");
102102
}
103103

104104
/** Initializes the peripherals clocks
105105
*/
106-
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG;
106+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
107+
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
107108
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
108109
PeriphClkInitStruct.RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE;
109110
PeriphClkInitStruct.SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE;

‎targets/TARGET_STM/USBPhyHw.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -37,7 +37,7 @@
3737
#if MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG
3838

3939
#if defined(TARGET_STM32F3) || defined(TARGET_STM32WB)
40-
#define USBHAL_IRQn USB_HP_IRQn
40+
#define USBHAL_IRQn USB_LP_IRQn
4141
#else
4242
#define USBHAL_IRQn USB_IRQn
4343
#endif
@@ -50,7 +50,7 @@
5050

5151
#endif
5252

53-
#define NB_ENDPOINT 16
53+
#define NB_ENDPOINT 8
5454

5555
// #define MAXTRANSFER_SIZE 0x200
5656
#define MAX_PACKET_SIZE_SETUP (48)

‎targets/TARGET_STM/USBPhy_STM32.cpp

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ static const uint32_t tx_ep_sizes[NUM_ENDPOINTS] = {
3939
MAX_PACKET_SIZE_ISO
4040
};
4141

42+
#if (MBED_CONF_TARGET_USB_SPEED != USE_USB_NO_OTG)
4243
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
4344
{
4445
uint32_t len;
@@ -49,15 +50,23 @@ uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
4950
}
5051
return len * 4;
5152
}
53+
#endif
5254

55+
/* weak function redefinition */
5356
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
5457
{
5558
USBPhyHw *priv = ((USBPhyHw *)(hpcd->pData));
59+
#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG)
60+
if (priv->sof_enabled) {
61+
priv->events->sof((hpcd->Instance->FNR) & USB_FNR_FN);
62+
}
63+
#else
5664
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
5765
uint32_t USBx_BASE = (uint32_t)USBx;
5866
if (priv->sof_enabled) {
5967
priv->events->sof((USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8);
6068
}
69+
#endif
6170
}
6271

6372
/* this call at device reception completion on a Out Enpoint */
@@ -244,7 +253,37 @@ void USBPhyHw::init(USBPhyEvents *events)
244253
HAL_StatusTypeDef ret = HAL_PCD_Init(&hpcd);
245254
MBED_ASSERT(ret == HAL_OK);
246255

256+
// Configure FIFOs
257+
#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG)
258+
259+
// EP0
260+
#define PMA_EP0_OUT_ADDR (8 * 4)
261+
#define PMA_EP0_IN_ADDR (PMA_EP0_OUT_ADDR + MAX_PACKET_SIZE_EP0)
262+
HAL_PCDEx_PMAConfig(&hpcd, LOG_OUT_TO_EP(0), PCD_SNG_BUF, PMA_EP0_OUT_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
263+
HAL_PCDEx_PMAConfig(&hpcd, LOG_IN_TO_EP(0), PCD_SNG_BUF, PMA_EP0_IN_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
264+
// EP1
265+
#define PMA_EP1_OUT_BASE (PMA_EP0_IN_ADDR + MAX_PACKET_SIZE_EP0)
266+
#define PMA_EP1_OUT_ADDR ((PMA_EP1_OUT_BASE + MAX_PACKET_SIZE_NON_ISO) | (PMA_EP1_OUT_BASE << 16U))
267+
#define PMA_EP1_IN_ADDR (PMA_EP1_OUT_BASE + MAX_PACKET_SIZE_NON_ISO)
268+
#define PMA_EP1_CMD_ADDR (PMA_EP1_IN_ADDR + MAX_PACKET_SIZE_NON_ISO)
269+
HAL_PCDEx_PMAConfig(&hpcd, LOG_OUT_TO_EP(1), PCD_SNG_BUF, PMA_EP1_OUT_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
270+
HAL_PCDEx_PMAConfig(&hpcd, LOG_IN_TO_EP(1), PCD_SNG_BUF, PMA_EP1_CMD_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
271+
// EP2
272+
#define PMA_EP2_OUT_BASE (PMA_EP1_IN_ADDR + MAX_PACKET_SIZE_NON_ISO)
273+
#define PMA_EP2_OUT_ADDR ((PMA_EP2_OUT_BASE + MAX_PACKET_SIZE_NON_ISO) | (PMA_EP2_OUT_BASE << 16U))
274+
#define PMA_EP2_IN_ADDR (PMA_EP2_OUT_BASE + MAX_PACKET_SIZE_NON_ISO * 2)
275+
#define PMA_EP2_CMD_ADDR (PMA_EP2_IN_ADDR + MAX_PACKET_SIZE_NON_ISO)
276+
HAL_PCDEx_PMAConfig(&hpcd, LOG_OUT_TO_EP(2), PCD_DBL_BUF, PMA_EP2_OUT_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
277+
HAL_PCDEx_PMAConfig(&hpcd, LOG_IN_TO_EP(2), PCD_SNG_BUF, PMA_EP2_CMD_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
278+
// EP3
279+
#define PMA_EP3_OUT_BASE (PMA_EP2_IN_ADDR + MAX_PACKET_SIZE_NON_ISO)
280+
#define PMA_EP3_OUT_ADDR ((PMA_EP3_OUT_BASE + MAX_PACKET_SIZE_ISO) | (PMA_EP3_OUT_BASE << 16U))
281+
#define PMA_EP3_IN_ADDR (PMA_EP3_OUT_BASE + MAX_PACKET_SIZE_ISO)
282+
#define PMA_EP3_CMD_ADDR (PMA_EP3_IN_ADDR + MAX_PACKET_SIZE_ISO)
283+
HAL_PCDEx_PMAConfig(&hpcd, LOG_OUT_TO_EP(3), PCD_SNG_BUF, PMA_EP3_OUT_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
284+
HAL_PCDEx_PMAConfig(&hpcd, LOG_IN_TO_EP(3), PCD_SNG_BUF, PMA_EP3_CMD_ADDR); // HAL_PCDEx_PMAConfig always returns HAL_OK
247285

286+
#else
248287
uint32_t total_bytes = 0;
249288

250289
/* Reserve space in the RX buffer for:
@@ -266,6 +305,7 @@ void USBPhyHw::init(USBPhyEvents *events)
266305

267306
/* 1.25 kbytes */
268307
MBED_ASSERT(total_bytes <= 1280);
308+
#endif
269309

270310
// Configure interrupt vector
271311
NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
@@ -293,8 +333,21 @@ bool USBPhyHw::powered()
293333

294334
void USBPhyHw::connect()
295335
{
336+
#if (MBED_CONF_TARGET_USB_SPEED == USE_USB_NO_OTG)
337+
DigitalOut usb_disc_pin(USB_DP, 1) ;
338+
wait_ns(1000);
339+
usb_disc_pin = 0;
340+
341+
uint32_t wInterrupt_Mask = USB_CNTR_CTRM | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM |
342+
USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_RESETM;
343+
/*Set interrupt mask*/
344+
hpcd.Instance->CNTR = wInterrupt_Mask;
345+
HAL_PCD_DevConnect(&hpcd); // HAL_PCD_DevConnect always return HAL_OK
346+
wait_us(10000);
347+
#else
296348
HAL_StatusTypeDef ret = HAL_PCD_Start(&hpcd);
297349
MBED_ASSERT(ret == HAL_OK);
350+
#endif
298351
}
299352

300353
void USBPhyHw::disconnect()
@@ -405,6 +458,7 @@ void USBPhyHw::ep0_stall()
405458

406459
bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_t type)
407460
{
461+
#if (MBED_CONF_TARGET_USB_SPEED != USE_USB_NO_OTG)
408462
uint32_t len;
409463

410464
/*
@@ -415,6 +469,8 @@ bool USBPhyHw::endpoint_add(usb_ep_t endpoint, uint32_t max_packet, usb_ep_type_
415469
len = HAL_PCDEx_GetTxFiFo(&hpcd, endpoint & 0x7f);
416470
MBED_ASSERT(len >= max_packet);
417471
}
472+
#endif
473+
418474
HAL_StatusTypeDef ret = HAL_PCD_EP_Open(&hpcd, endpoint, max_packet, type);
419475
MBED_ASSERT(ret != HAL_BUSY);
420476
return (ret == HAL_OK) ? true : false;

‎targets/targets.json

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4126,6 +4126,7 @@
41264126
"SERIAL_FC",
41274127
"TRNG",
41284128
"FLASH",
4129+
"USBDEVICE",
41294130
"MPU"
41304131
],
41314132
"device_name": "STM32WB55RGVx",

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