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Lines changed: 1 addition & 81 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,5 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2018 Gigadevice
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* Copyright (c) 2018 GigaDevice Semiconductor Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
@@ -76,82 +75,3 @@ void enet_bsp_init(void)
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rcu_periph_clock_enable(RCU_ENETTX);
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rcu_periph_clock_enable(RCU_ENETRX);
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}
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=======
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/* mbed Microcontroller Library
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* Copyright (c) 2018 Gigadevice Semiconductor Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "gd32f30x.h"
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/**
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* Initializes the HW pin for enet
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*
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*/
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void enet_bsp_init(void)
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{
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/* Enable GPIOs clocks */
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rcu_periph_clock_enable(RCU_GPIOA);
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rcu_periph_clock_enable(RCU_GPIOB);
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rcu_periph_clock_enable(RCU_GPIOC);
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rcu_periph_clock_enable(RCU_AF);
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gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_8);
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rcu_pll2_config(RCU_PLL2_MUL10);
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rcu_osci_on(RCU_PLL2_CK);
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rcu_osci_stab_wait(RCU_PLL2_CK);
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rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2);
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gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII);
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/** ETH GPIO Configuration
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RMII_REF_CLK ----------------------> PA1
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RMII_MDIO -------------------------> PA2
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RMII_MDC --------------------------> PC1
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RMII_MII_CRS_DV -------------------> PA7
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RMII_MII_RXD0 ---------------------> PC4
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RMII_MII_RXD1 ---------------------> PC5
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RMII_MII_TX_EN --------------------> PB11
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RMII_MII_TXD0 ---------------------> PB12
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RMII_MII_TXD1 ---------------------> PB13
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*/
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/* PA1: ETH_RMII_REF_CLK */
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gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_1);
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/* PA2: ETH_MDIO */
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gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_2);
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/* PA7: ETH_RMII_CRS_DV */
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gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_7);
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/* PB11: ETH_RMII_TX_EN */
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gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_11);
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/* PB12: ETH_RMII_TXD0 */
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gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_12);
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/* PB13: ETH_RMII_TXD1 */
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gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_13);
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/* PC1: ETH_MDC */
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gpio_para_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_1);
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/* PC4: ETH_RMII_RXD0 */
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gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_4);
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/* PC5: ETH_RMII_RXD1 */
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gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_5);
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/* Enable the Ethernet global Interrupt */
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nvic_irq_enable(ENET_IRQn, 0x7, 0);
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/* Enable ETHERNET clock */
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rcu_periph_clock_enable(RCU_ENET);
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rcu_periph_clock_enable(RCU_ENETTX);
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rcu_periph_clock_enable(RCU_ENETRX);
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}
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>>>>>>> 644cc537cff06b20c3155fe0dea2ac62d567c3c3

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