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1 |
| -<<<<<<< HEAD |
2 | 1 | /* mbed Microcontroller Library
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3 |
| - * Copyright (c) 2018 Gigadevice |
| 2 | + * Copyright (c) 2018 GigaDevice Semiconductor Inc. |
4 | 3 | *
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5 | 4 | * Licensed under the Apache License, Version 2.0 (the "License");
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6 | 5 | * you may not use this file except in compliance with the License.
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@@ -76,82 +75,3 @@ void enet_bsp_init(void)
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76 | 75 | rcu_periph_clock_enable(RCU_ENETTX);
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77 | 76 | rcu_periph_clock_enable(RCU_ENETRX);
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78 | 77 | }
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79 |
| -======= |
80 |
| -/* mbed Microcontroller Library |
81 |
| - * Copyright (c) 2018 Gigadevice Semiconductor Inc. |
82 |
| - * |
83 |
| - * Licensed under the Apache License, Version 2.0 (the "License"); |
84 |
| - * you may not use this file except in compliance with the License. |
85 |
| - * You may obtain a copy of the License at |
86 |
| - * |
87 |
| - * http://www.apache.org/licenses/LICENSE-2.0 |
88 |
| - * |
89 |
| - * Unless required by applicable law or agreed to in writing, software |
90 |
| - * distributed under the License is distributed on an "AS IS" BASIS, |
91 |
| - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
92 |
| - * See the License for the specific language governing permissions and |
93 |
| - * limitations under the License. |
94 |
| - */ |
95 |
| - |
96 |
| -#include "gd32f30x.h" |
97 |
| - |
98 |
| -/** |
99 |
| - * Initializes the HW pin for enet |
100 |
| - * |
101 |
| - */ |
102 |
| -void enet_bsp_init(void) |
103 |
| -{ |
104 |
| - /* Enable GPIOs clocks */ |
105 |
| - rcu_periph_clock_enable(RCU_GPIOA); |
106 |
| - rcu_periph_clock_enable(RCU_GPIOB); |
107 |
| - rcu_periph_clock_enable(RCU_GPIOC); |
108 |
| - rcu_periph_clock_enable(RCU_AF); |
109 |
| - |
110 |
| - gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_8); |
111 |
| - rcu_pll2_config(RCU_PLL2_MUL10); |
112 |
| - rcu_osci_on(RCU_PLL2_CK); |
113 |
| - rcu_osci_stab_wait(RCU_PLL2_CK); |
114 |
| - rcu_ckout0_config(RCU_CKOUT0SRC_CKPLL2); |
115 |
| - gpio_ethernet_phy_select(GPIO_ENET_PHY_RMII); |
116 |
| - |
117 |
| - /** ETH GPIO Configuration |
118 |
| - RMII_REF_CLK ----------------------> PA1 |
119 |
| - RMII_MDIO -------------------------> PA2 |
120 |
| - RMII_MDC --------------------------> PC1 |
121 |
| - RMII_MII_CRS_DV -------------------> PA7 |
122 |
| - RMII_MII_RXD0 ---------------------> PC4 |
123 |
| - RMII_MII_RXD1 ---------------------> PC5 |
124 |
| - RMII_MII_TX_EN --------------------> PB11 |
125 |
| - RMII_MII_TXD0 ---------------------> PB12 |
126 |
| - RMII_MII_TXD1 ---------------------> PB13 |
127 |
| - */ |
128 |
| - /* PA1: ETH_RMII_REF_CLK */ |
129 |
| - gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_1); |
130 |
| - /* PA2: ETH_MDIO */ |
131 |
| - gpio_para_init(GPIOA, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_2); |
132 |
| - /* PA7: ETH_RMII_CRS_DV */ |
133 |
| - gpio_para_init(GPIOA, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_7); |
134 |
| - |
135 |
| - /* PB11: ETH_RMII_TX_EN */ |
136 |
| - gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_11); |
137 |
| - /* PB12: ETH_RMII_TXD0 */ |
138 |
| - gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_12); |
139 |
| - /* PB13: ETH_RMII_TXD1 */ |
140 |
| - gpio_para_init(GPIOB, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_13); |
141 |
| - |
142 |
| - /* PC1: ETH_MDC */ |
143 |
| - gpio_para_init(GPIOC, GPIO_MODE_AF_PP, GPIO_OSPEED_MAX, GPIO_PIN_1); |
144 |
| - /* PC4: ETH_RMII_RXD0 */ |
145 |
| - gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_4); |
146 |
| - /* PC5: ETH_RMII_RXD1 */ |
147 |
| - gpio_para_init(GPIOC, GPIO_MODE_IN_FLOATING, GPIO_OSPEED_MAX, GPIO_PIN_5); |
148 |
| - |
149 |
| - /* Enable the Ethernet global Interrupt */ |
150 |
| - nvic_irq_enable(ENET_IRQn, 0x7, 0); |
151 |
| - |
152 |
| - /* Enable ETHERNET clock */ |
153 |
| - rcu_periph_clock_enable(RCU_ENET); |
154 |
| - rcu_periph_clock_enable(RCU_ENETTX); |
155 |
| - rcu_periph_clock_enable(RCU_ENETRX); |
156 |
| -} |
157 |
| ->>>>>>> 644cc537cff06b20c3155fe0dea2ac62d567c3c3 |
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