F2 CUBE V1.6.0

This PR updates STM32 Cube SDK to
- HAL V1.2.1
- LL V1.2.1
- CMSIS 2.2.0

Author: LMESTM

targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/stm32f207xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    stm32f2xx.h
   * @author  MCD Application Team
-  * @version V2.1.2
-  * @date    29-June-2016
+  * @version V2.2.0
+  * @date    17-March-2017
   * @brief   CMSIS STM32F2xx Device Peripheral Access Layer Header File.
   *
   *          The file is the unique include file that the application programmer
@@ -18,7 +18,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -99,11 +99,11 @@ extern "C" {
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.1.2
+  * @brief CMSIS Device version number V2.2.0
   */
 #define __STM32F2xx_CMSIS_VERSION_MAIN   (0x02U) /*!< [31:24] main version */
-#define __STM32F2xx_CMSIS_VERSION_SUB1   (0x01U) /*!< [23:16] sub1 version */
-#define __STM32F2xx_CMSIS_VERSION_SUB2   (0x02U) /*!< [15:8]  sub2 version */
+#define __STM32F2xx_CMSIS_VERSION_SUB1   (0x02U) /*!< [23:16] sub1 version */
+#define __STM32F2xx_CMSIS_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F2xx_CMSIS_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F2xx_CMSIS_VERSION        ((__STM32F2xx_CMSIS_VERSION_MAIN << 24)\
                                          |(__STM32F2xx_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/stm32f2xx.h

@@ -2,8 +2,8 @@
   ******************************************************************************
   * @file    system_stm32f2xx.c
   * @author  MCD Application Team
-  * @version V2.1.2
-  * @date    29-June-2016
+  * @version V2.2.0
+  * @date    17-March-2017
   * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
   *
   *   This file provides two functions and one global variable to be called from
@@ -39,7 +39,7 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT 2016 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -127,18 +127,18 @@
 /** @addtogroup STM32F2xx_System_Private_Variables
   * @{
   */
-
-/* This variable can be updated in Three ways :
-    1) by calling CMSIS function SystemCoreClockUpdate()
-    2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-    3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-       Note: If you use this function to configure the system clock; then there
-             is no need to call the 2 first functions listed above, since SystemCoreClock
-             variable is updated automatically.
-*/
-uint32_t SystemCoreClock = 120000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
+  
+  /* This variable can be updated in Three ways :
+      1) by calling CMSIS function SystemCoreClockUpdate()
+      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
+         Note: If you use this function to configure the system clock; then there
+               is no need to call the 2 first functions listed above, since SystemCoreClock
+               variable is updated automatically.
+  */
+  uint32_t SystemCoreClock = 16000000;
+  const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+  const uint8_t APBPrescTable[8]  = {0, 0, 0, 0, 1, 2, 3, 4};
 /**
   * @}
   */
@@ -148,7 +148,7 @@ const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8,
   */
 
 #ifdef DATA_IN_ExtSRAM
-static void SystemInit_ExtMemCtl(void);
+  static void SystemInit_ExtMemCtl(void); 
 #endif /* DATA_IN_ExtSRAM */
 
 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -166,41 +166,41 @@ uint8_t SetSysClock_PLL_HSI(void);
 
 /**
   * @brief  Setup the microcontroller system
-  *         Initialize the Embedded Flash Interface, the PLL and update the
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
   *         SystemFrequency variable.
   * @param  None
   * @retval None
   */
 void SystemInit(void)
 {
-    /* Reset the RCC clock configuration to the default reset state ------------*/
-    /* Set HSION bit */
-    RCC->CR |= (uint32_t)0x00000001;
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
 
-    /* Reset CFGR register */
-    RCC->CFGR = 0x00000000;
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
 
-    /* Reset HSEON, CSSON and PLLON bits */
-    RCC->CR &= (uint32_t)0xFEF6FFFF;
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
 
-    /* Reset PLLCFGR register */
-    RCC->PLLCFGR = 0x24003010;
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
 
-    /* Reset HSEBYP bit */
-    RCC->CR &= (uint32_t)0xFFFBFFFF;
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
 
-    /* Disable all interrupts */
-    RCC->CIR = 0x00000000;
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
 
 #ifdef DATA_IN_ExtSRAM
-    SystemInit_ExtMemCtl();
+  SystemInit_ExtMemCtl(); 
 #endif /* DATA_IN_ExtSRAM */
 
-    /* Configure the Vector Table location add offset address ------------------*/
+  /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
-    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
-    SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 #endif
 
 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@@ -224,24 +224,83 @@ void SystemInit(void)
   *         The SystemCoreClock variable contains the core clock (HCLK), it can
   *         be used by the user application to setup the SysTick timer or configure
   *         other parameters.
-  *
+  *           
   * @note   Each time the core clock (HCLK) changes, this function must be called
   *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.
-  *
-  * @note   - The system frequency computed by this function is not the real
-  *           frequency in the chip. It is calculated based on the predefined
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
   *           constant and the selected clock source:
-  *
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value
+  *              depends on the application requirements), user has to ensure that HSE_VALUE
+  *              is same as the real frequency of the crystal used. Otherwise, this function
+  *              may have wrong result.
+  *                
   *         - The result of this function could be not correct when using fractional
   *           value for HSE crystal.
-  *
+  *     
   * @param  None
   * @retval None
   */
 void SystemCoreClockUpdate(void)
 {
-    SystemCoreClock = HAL_RCC_GetSysClockFreq();
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
 }
 
 #ifdef DATA_IN_ExtSRAM
@@ -255,71 +314,71 @@ void SystemCoreClockUpdate(void)
   */
 void SystemInit_ExtMemCtl(void)
 {
-    __IO uint32_t tmp = 0x00;
-
-    /*-- GPIOs Configuration -----------------------------------------------------*/
-    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-    RCC->AHB1ENR   |= 0x00000078;
-    /* Delay after an RCC peripheral clock enabling */
-    tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
-    (void)(tmp);
-
-    /* Connect PDx pins to FSMC Alternate function */
-    GPIOD->AFR[0]  = 0x00CCC0CC;
-    GPIOD->AFR[1]  = 0xCCCCCCCC;
-    /* Configure PDx pins in Alternate function mode */
-    GPIOD->MODER   = 0xAAAA0A8A;
-    /* Configure PDx pins speed to 100 MHz */
-    GPIOD->OSPEEDR = 0xFFFF0FCF;
-    /* Configure PDx pins Output type to push-pull */
-    GPIOD->OTYPER  = 0x00000000;
-    /* No pull-up, pull-down for PDx pins */
-    GPIOD->PUPDR   = 0x00000000;
-
-    /* Connect PEx pins to FSMC Alternate function */
-    GPIOE->AFR[0]  = 0xC00CC0CC;
-    GPIOE->AFR[1]  = 0xCCCCCCCC;
-    /* Configure PEx pins in Alternate function mode */
-    GPIOE->MODER   = 0xAAAA828A;
-    /* Configure PEx pins speed to 100 MHz */
-    GPIOE->OSPEEDR = 0xFFFFC3CF;
-    /* Configure PEx pins Output type to push-pull */
-    GPIOE->OTYPER  = 0x00000000;
-    /* No pull-up, pull-down for PEx pins */
-    GPIOE->PUPDR   = 0x00000000;
-
-    /* Connect PFx pins to FSMC Alternate function */
-    GPIOF->AFR[0]  = 0x00CCCCCC;
-    GPIOF->AFR[1]  = 0xCCCC0000;
-    /* Configure PFx pins in Alternate function mode */
-    GPIOF->MODER   = 0xAA000AAA;
-    /* Configure PFx pins speed to 100 MHz */
-    GPIOF->OSPEEDR = 0xFF000FFF;
-    /* Configure PFx pins Output type to push-pull */
-    GPIOF->OTYPER  = 0x00000000;
-    /* No pull-up, pull-down for PFx pins */
-    GPIOF->PUPDR   = 0x00000000;
-
-    /* Connect PGx pins to FSMC Alternate function */
-    GPIOG->AFR[0]  = 0x00CCCCCC;
-    GPIOG->AFR[1]  = 0x000000C0;
-    /* Configure PGx pins in Alternate function mode */
-    GPIOG->MODER   = 0x00085AAA;
-    /* Configure PGx pins speed to 100 MHz */
-    GPIOG->OSPEEDR = 0x000CAFFF;
-    /* Configure PGx pins Output type to push-pull */
-    GPIOG->OTYPER  = 0x00000000;
-    /* No pull-up, pull-down for PGx pins */
-    GPIOG->PUPDR   = 0x00000000;
-
-    /*--FSMC Configuration -------------------------------------------------------*/
-    /* Enable the FSMC interface clock */
-    RCC->AHB3ENR         |= 0x00000001;
-
-    /* Configure and enable Bank1_SRAM2 */
-    FSMC_Bank1->BTCR[2]  = 0x00001011;
-    FSMC_Bank1->BTCR[3]  = 0x00000201;
-    FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
+  __IO uint32_t tmp = 0x00;
+
+/*-- GPIOs Configuration -----------------------------------------------------*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   |= 0x00000078;
+  /* Delay after an RCC peripheral clock enabling */
+  tmp = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);
+  (void)(tmp);
+
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00CCC0CC;
+  GPIOD->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xAAAA0A8A;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xFFFF0FCF;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xC00CC0CC;
+  GPIOE->AFR[1]  = 0xCCCCCCCC;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xAAAA828A;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xFFFFC3CF;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00CCCCCC;
+  GPIOF->AFR[1]  = 0xCCCC0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xAA000AAA;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xFF000FFF;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00CCCCCC;
+  GPIOG->AFR[1]  = 0x000000C0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00085AAA;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000CAFFF;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*--FSMC Configuration -------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         |= 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001011;
+  FSMC_Bank1->BTCR[3]  = 0x00000201;
+  FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
 }
 #endif /* DATA_IN_ExtSRAM */