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Tauno Magnusson
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Adding support for NUCLEO_G431KB. Created this file based on G474RE file. Added support for USB - connected the HSI48 clock to USB (and RNG). Warning: I'm assuming Flash latency is the same as for G474RE.
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‎targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G431xB/system_clock.c

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/* mbed Microcontroller Library
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* SPDX-License-Identifier: BSD-3-Clause
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******************************************************************************
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/**
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------
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* System clock source | 1- USE_PLL_HSE_EXTC (external 8 MHz clock)
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* | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
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* | 3- USE_PLL_HSI (internal 16 MHz)
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*-----------------------------------------------------------------
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* SYSCLK(MHz) | 64
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* AHBCLK (MHz) | 64
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* APB1CLK (MHz) | 64
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* USB capable | NO
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*-----------------------------------------------------------------
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*/
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#include "stm32g4xx.h"
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#include "mbed_error.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
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This value must be a multiple of 0x100. */
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
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/* 1- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
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/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0)
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#endif
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{
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{
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error("SetSysClock failed\n");
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}
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}
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}
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
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}
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#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV6;
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//! 170MHz as a core frequency for FDCAN is not suitable for many frequencies,
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//! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz
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//! should be standard.
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#if DEVICE_CAN
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RCC_OscInitStruct.PLL.PLLN = 80;
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#else
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RCC_OscInitStruct.PLL.PLLN = 85;
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#endif
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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// For USB: Default to USB driven by HSI48 Clock. (USB needs a 48 MHz Clock).
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// Code below enables the HSI48 Clock
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// (Sidenote: RNG is also driven (and according to STM specs) verified with the 48MHz HSI48)
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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// For USB: Default to USB driven by HSI48 Clock.
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// Code below connects USB (and RNG) to the HSI48 Clock.
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RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
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RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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// This is an assumption: Using same Flash Latency as for G474RE
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) {
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return 0; // FAIL
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}
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_OscInitTypeDef RCC_OscInitStruct = {0};
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RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
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RCC_PeriphCLKInitTypeDef RCC_PeriphCLKInitStruct = { 0 };
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/** Configure the main internal regulator output voltage
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*/
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HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
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RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
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RCC_OscInitStruct.PLL.PLLN = 85;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
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RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
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RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48; // Enable HSI48 and feed it to USB/RNG.
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RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; // USB needs - and RNG is verified with - the 48Mhz HSI48.
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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RCC_PeriphCLKInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB; // Connect HSI48 clock to USB (and RNG)
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RCC_PeriphCLKInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
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if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphCLKInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/** Initializes the CPU, AHB and APB busses clocks
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*/
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RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
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| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) {
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return 0; // FAIL
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}
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return 1; // OK
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}
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */

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