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L0 ST CUBE V1.10.0: spi and i2c corrections
1 parent 8191487 commit 61576f8

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4 files changed

+21
-173
lines changed

4 files changed

+21
-173
lines changed

‎targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_def.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -203,3 +203,4 @@ typedef enum
203203
#endif /* ___STM32L0xx_HAL_DEF */
204204

205205
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
206+

‎targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.c

Lines changed: 12 additions & 103 deletions
Original file line numberDiff line numberDiff line change
@@ -348,10 +348,6 @@ static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32
348348
static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
349349
static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
350350

351-
/* Private functions to centralize the enable/disable of Interrupts */
352-
static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
353-
static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
354-
355351
/* Private functions to flush TXDR register */
356352
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
357353

@@ -2158,10 +2154,6 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
21582154
hi2c->Mode = HAL_I2C_MODE_MEM;
21592155
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
21602156

2161-
/* Prepare transfer parameters */
2162-
hi2c->Mode = HAL_I2C_MODE_MEM;
2163-
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2164-
21652157
/* Prepare transfer parameters */
21662158
hi2c->pBuffPtr = pData;
21672159
hi2c->XferCount = Size;
@@ -2600,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
26002592
/* Prepare transfer parameters */
26012593
hi2c->pBuffPtr = pData;
26022594
hi2c->XferCount = Size;
2603-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
2595+
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED commit 23926a2418
26042596
hi2c->XferISR = I2C_Master_ISR_IT;
26052597

26062598
/* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2615,12 +2607,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
26152607
xfermode = hi2c->XferOptions;
26162608
}
26172609

2610+
// MBED commit 23926a2418
26182611
/* If transfer direction not change, do not generate Restart Condition */
26192612
/* Mean Previous state is same as current state */
2620-
if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
2621-
{
2622-
xferrequest = I2C_NO_STARTSTOP;
2623-
}
2613+
//if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
2614+
//{
2615+
// xferrequest = I2C_NO_STARTSTOP;
2616+
//}
26242617

26252618
/* Send Slave Address and set NBYTES to write */
26262619
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
@@ -2673,7 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
26732666
/* Prepare transfer parameters */
26742667
hi2c->pBuffPtr = pData;
26752668
hi2c->XferCount = Size;
2676-
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
2669+
hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED commit 23926a2418
26772670
hi2c->XferISR = I2C_Master_ISR_IT;
26782671

26792672
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
@@ -2688,12 +2681,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
26882681
xfermode = hi2c->XferOptions;
26892682
}
26902683

2684+
// MBED commit 23926a2418
26912685
/* If transfer direction not change, do not generate Restart Condition */
26922686
/* Mean Previous state is same as current state */
2693-
if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
2694-
{
2695-
xferrequest = I2C_NO_STARTSTOP;
2696-
}
2687+
//if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
2688+
//{
2689+
// xferrequest = I2C_NO_STARTSTOP;
2690+
//}
26972691

26982692
/* Send Slave Address and set NBYTES to read */
26992693
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
@@ -2983,13 +2977,6 @@ void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
29832977

29842978
/* I2C events treatment -------------------------------------*/
29852979
if (hi2c->XferISR != NULL)
2986-
{
2987-
hi2c->XferISR(hi2c, itflags, itsources);
2988-
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
2989-
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
2990-
2991-
/* I2C events treatment -------------------------------------*/
2992-
if(hi2c->XferISR != NULL)
29932980
{
29942981
hi2c->XferISR(hi2c, itflags, itsources);
29952982
}
@@ -3584,11 +3571,6 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
35843571
/* Call I2C Master complete process */
35853572
I2C_ITMasterCplt(hi2c, ITFlags);
35863573
}
3587-
else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3588-
{
3589-
/* Call I2C Master complete process */
3590-
I2C_ITMasterCplt(hi2c, ITFlags);
3591-
}
35923574

35933575
/* Process Unlocked */
35943576
__HAL_UNLOCK(hi2c);
@@ -4794,79 +4776,6 @@ static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t Interr
47944776
return HAL_OK;
47954777
}
47964778

4797-
/**
4798-
* @brief Manage the disabling of Interrupts.
4799-
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4800-
* the configuration information for the specified I2C.
4801-
* @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
4802-
* @retval HAL status
4803-
*/
4804-
static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
4805-
{
4806-
uint32_t tmpisr = 0U;
4807-
4808-
if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
4809-
(hi2c->XferISR == I2C_Slave_ISR_DMA))
4810-
{
4811-
if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4812-
{
4813-
/* Enable ERR, STOP, NACK and ADDR interrupts */
4814-
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4815-
}
4816-
4817-
if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
4818-
{
4819-
/* Enable ERR and NACK interrupts */
4820-
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
4821-
}
4822-
4823-
if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4824-
{
4825-
/* Enable STOP interrupts */
4826-
tmpisr |= I2C_IT_STOPI;
4827-
}
4828-
4829-
if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
4830-
{
4831-
/* Enable TC interrupts */
4832-
tmpisr |= I2C_IT_TCI;
4833-
}
4834-
}
4835-
else
4836-
{
4837-
if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4838-
{
4839-
/* Enable ERR, STOP, NACK, and ADDR interrupts */
4840-
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4841-
}
4842-
4843-
if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
4844-
{
4845-
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
4846-
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
4847-
}
4848-
4849-
if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
4850-
{
4851-
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
4852-
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
4853-
}
4854-
4855-
if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4856-
{
4857-
/* Enable STOP interrupts */
4858-
tmpisr |= I2C_IT_STOPI;
4859-
}
4860-
}
4861-
4862-
/* Enable interrupts only at the end */
4863-
/* to avoid the risk of I2C interrupt handle execution before */
4864-
/* all interrupts requested done */
4865-
__HAL_I2C_ENABLE_IT(hi2c, tmpisr);
4866-
4867-
return HAL_OK;
4868-
}
4869-
48704779
/**
48714780
* @brief Manage the disabling of Interrupts.
48724781
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains

‎targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_i2c.h

Lines changed: 0 additions & 69 deletions
Original file line numberDiff line numberDiff line change
@@ -225,8 +225,6 @@ typedef struct __I2C_HandleTypeDef
225225

226226
__IO uint32_t ErrorCode; /*!< I2C Error code */
227227

228-
__IO uint32_t ErrorCode; /*!< I2C Error code */
229-
230228
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
231229
} I2C_HandleTypeDef;
232230
/**
@@ -621,73 +619,6 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
621619

622620
/* Private macros ------------------------------------------------------------*/
623621
/** @defgroup I2C_Private_Macro I2C Private Macros
624-
625-
/* Private macros ------------------------------------------------------------*/
626-
/** @defgroup I2C_Private_Macro I2C Private Macros
627-
* @{
628-
*/
629-
630-
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
631-
((MODE) == I2C_ADDRESSINGMODE_10BIT))
632-
633-
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
634-
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
635-
636-
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
637-
((MASK) == I2C_OA2_MASK01) || \
638-
((MASK) == I2C_OA2_MASK02) || \
639-
((MASK) == I2C_OA2_MASK03) || \
640-
((MASK) == I2C_OA2_MASK04) || \
641-
((MASK) == I2C_OA2_MASK05) || \
642-
((MASK) == I2C_OA2_MASK06) || \
643-
((MASK) == I2C_OA2_MASK07))
644-
645-
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
646-
((CALL) == I2C_GENERALCALL_ENABLE))
647-
648-
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
649-
((STRETCH) == I2C_NOSTRETCH_ENABLE))
650-
651-
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
652-
((SIZE) == I2C_MEMADD_SIZE_16BIT))
653-
654-
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
655-
((MODE) == I2C_AUTOEND_MODE) || \
656-
((MODE) == I2C_SOFTEND_MODE))
657-
658-
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
659-
((REQUEST) == I2C_GENERATE_START_READ) || \
660-
((REQUEST) == I2C_GENERATE_START_WRITE) || \
661-
((REQUEST) == I2C_NO_STARTSTOP))
662-
663-
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
664-
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
665-
((REQUEST) == I2C_NEXT_FRAME) || \
666-
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
667-
((REQUEST) == I2C_LAST_FRAME))
668-
669-
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
670-
671-
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U)
672-
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
673-
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
674-
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
675-
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
676-
677-
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
678-
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU)
679-
680-
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))
681-
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))
682-
683-
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
684-
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
685-
/**
686-
* @}
687-
*/
688-
689-
/* Private Functions ---------------------------------------------------------*/
690-
/** @defgroup I2C_Private_Functions I2C Private Functions
691622
* @{
692623
*/
693624

‎targets/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_spi.c

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -167,12 +167,13 @@
167167
* @{
168168
*/
169169
#define SPI_TIMEOUT_VALUE 10U
170-
#define SPI_DEFAULT_TIMEOUT 100U
170+
#define SPI_DEFAULT_TIMEOUT 100U // MBED commit 64a037cc
171171

172172
/* Private macro -------------------------------------------------------------*/
173173
/* Private variables ---------------------------------------------------------*/
174174
/* Private function prototypes -----------------------------------------------*/
175175

176+
// MBED commit 64a037cc
176177
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
177178
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
178179
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
@@ -1026,6 +1027,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u
10261027
hspi->State = HAL_SPI_STATE_BUSY_TX;
10271028
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
10281029

1030+
// MBED commit 64a037cc
10291031
/* Set the function for IT treatment */
10301032
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
10311033
{
@@ -1109,6 +1111,7 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui
11091111
hspi->State = HAL_SPI_STATE_BUSY_RX;
11101112
hspi->ErrorCode = HAL_SPI_ERROR_NONE;
11111113

1114+
// MBED commit 64a037cc
11121115
/* Set the function for IT treatment */
11131116
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
11141117
{
@@ -1216,6 +1219,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p
12161219
hspi->RxXferSize = Size;
12171220
hspi->RxXferCount = Size;
12181221

1222+
// MBED commit 64a037cc
12191223
/* Set the function for IT treatment */
12201224
if(hspi->Init.DataSize > SPI_DATASIZE_8BIT )
12211225
{
@@ -1861,6 +1865,8 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
18611865
* @{
18621866
*/
18631867

1868+
// MBED commit 64a037cc
1869+
18641870
/**
18651871
* @brief DMA SPI transmit process complete callback
18661872
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
@@ -2210,6 +2216,7 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin
22102216
* @}
22112217
*/
22122218

2219+
// MBED commit 64a037cc
22132220
/**
22142221
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
22152222
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains

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