Merge pull request #10660 from mprse/fpga_ts_add_sckl_stats

Add SCLK and SIN stats to SPIMasterTester

Author: 0xc0170

components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.cpp

@@ -68,3 +68,11 @@ uint32_t SPIMasterTester::get_last_clk_edge_to_cs_ns()
 
     return (delay_ns * 10);
 }
+
+uint8_t SPIMasterTester::get_start_stop_stats()
+{
+    uint8_t start_stop_stats;
+    read(TESTER_SPI_MASTER_START_STOP_STATS, (uint8_t *)&start_stop_stats, TESTER_SPI_MASTER_START_STOP_STATS_SIZE);
+
+    return start_stop_stats;
+}

components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/SPIMasterTester.h

@@ -104,6 +104,20 @@ class SPIMasterTester: public SPITester {
      */
     uint32_t get_last_clk_edge_to_cs_ns();
 
+    /**
+     * Get SCLK and SIN states on transmission start and stop.
+     *
+     *  @return latched SCLK and SIN states on transmission start and stop.
+     *
+     *  @note Stats are encoded as fallows (bit 0 - LSB):
+     *        - bit 0: start SCLK
+     *        - bit 1: start SIN
+     *        - bit 2: stop SCLK,
+     *        - bit 3: stop SIN,
+     *        - other: unused
+     */
+    uint8_t get_start_stop_stats();
+
 };
 
 #endif

components/testing/COMPONENT_FPGA_CI_TEST_SHIELD/fpga_config.h

@@ -56,6 +56,8 @@
 #define TESTER_SPI_MASTER_STOPS                       0x00102009
 #define TESTER_SPI_MASTER_TRANSFERS                   0x0010200A
 #define TESTER_SPI_MASTER_TRANSFERS_SIZE              2
+#define TESTER_SPI_MASTER_START_STOP_STATS            0x0010200C
+#define TESTER_SPI_MASTER_START_STOP_STATS_SIZE       1
 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM           0x00102012
 #define TESTER_SPI_MASTER_TO_SLAVE_CHECKSUM_SIZE      4
 #define TESTER_SPI_MASTER_CTRL                        0x00102016