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MIMXRT1050: Update to EVK Rev B
1. Add the IVT header to the binary as this is required for boot up This was earlier added by the DAPLink firmware. As it is no longer handled in DAPLink, the header needs to be added inside mbed. 2. Update drivers Signed-off-by: Mahesh Mahadevan <[email protected]>
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‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/device.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@
1919
#define MBED_DEVICE_H
2020

2121
#define DEVICE_ID_LENGTH 24
22+
#define BOARD_FLASH_SIZE (0x4000000U)
2223

2324
#include "objects.h"
2425

‎targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT1050/TARGET_EVK/fsl_clock_config.c

Lines changed: 254 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11
/*
2+
* The Clear BSD License
23
* Copyright 2017 NXP
4+
* All rights reserved.
35
*
46
* Redistribution and use in source and binary forms, with or without modification,
5-
* are permitted provided that the following conditions are met:
7+
* are permitted (subject to the limitations in the disclaimer below) provided
8+
* that the following conditions are met:
69
*
710
* o Redistributions of source code must retain the above copyright notice, this list
811
* of conditions and the following disclaimer.
@@ -15,6 +18,7 @@
1518
* contributors may be used to endorse or promote products derived from this
1619
* software without specific prior written permission.
1720
*
21+
* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
1822
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
1923
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
2024
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -26,21 +30,36 @@
2630
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
2731
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
2832
*/
33+
/*
34+
* How to setup clock using clock driver functions:
35+
*
36+
* 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
37+
*
38+
* 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
39+
*
40+
* 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
41+
*
42+
* 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
43+
*
44+
* 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
45+
*
46+
*/
47+
48+
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
49+
!!GlobalInfo
50+
product: Clocks v4.1
51+
processor: MIMXRT1052xxxxB
52+
package_id: MIMXRT1052DVL6B
53+
mcu_data: ksdk2_0
54+
processor_version: 0.0.0
55+
board: IMXRT1050-EVKB
56+
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
2957

30-
#include "fsl_common.h"
3158
#include "fsl_clock_config.h"
3259

3360
/*******************************************************************************
3461
* Definitions
3562
******************************************************************************/
36-
/* ARM PLL configuration for RUN mode */
37-
const clock_arm_pll_config_t armPllConfig = {.loopDivider = 100U};
38-
39-
/* SYS PLL configuration for RUN mode */
40-
const clock_sys_pll_config_t sysPllConfig = {.loopDivider = 1U};
41-
42-
/* USB1 PLL configuration for RUN mode */
43-
const clock_usb_pll_config_t usb1PllConfig = {.loopDivider = 0U};
4463

4564
/*******************************************************************************
4665
* Variables
@@ -49,59 +68,240 @@ const clock_usb_pll_config_t usb1PllConfig = {.loopDivider = 0U};
4968
extern uint32_t SystemCoreClock;
5069

5170
/*******************************************************************************
52-
* Code
71+
************************ BOARD_InitBootClocks function ************************
5372
******************************************************************************/
54-
static void BOARD_BootClockGate(void)
73+
void BOARD_InitBootClocks(void)
5574
{
56-
/* Disable all unused peripheral clock */
57-
CCM->CCGR0 = 0x00C0000FU;
58-
CCM->CCGR1 = 0x30000000U;
59-
CCM->CCGR2 = 0xFF3F303FU;
60-
CCM->CCGR3 = 0xF0000330U;
61-
CCM->CCGR4 = 0x0000FF3CU;
62-
CCM->CCGR5 = 0xF003330FU;
63-
CCM->CCGR6 = 0x00FC0F00U;
75+
BOARD_BootClockRUN();
6476
}
6577

78+
/*******************************************************************************
79+
********************** Configuration BOARD_BootClockRUN ***********************
80+
******************************************************************************/
81+
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
82+
!!Configuration
83+
name: BOARD_BootClockRUN
84+
called_from_default_init: true
85+
outputs:
86+
- {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
87+
- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
88+
- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
89+
- {id: CLK_1M.outFreq, value: 1 MHz}
90+
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
91+
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
92+
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
93+
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
94+
- {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
95+
- {id: FLEXSPI_CLK_ROOT.outFreq, value: 37.5 MHz}
96+
- {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
97+
- {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
98+
- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
99+
- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
100+
- {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
101+
- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
102+
- {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
103+
- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
104+
- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
105+
- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
106+
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
107+
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
108+
- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
109+
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
110+
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
111+
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
112+
settings:
113+
- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
114+
- {id: CCM.ARM_PODF.scale, value: '2', locked: true}
115+
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
116+
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
117+
- {id: CCM.SEMC_PODF.scale, value: '8'}
118+
- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
119+
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
120+
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
121+
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
122+
- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
123+
- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
124+
- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
125+
- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
126+
- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
127+
- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
128+
- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
129+
- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
130+
- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
131+
- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
132+
- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
133+
- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
134+
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
135+
- {id: CCM_ANALOG.PLL4.div, value: '47'}
136+
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
137+
- {id: CCM_ANALOG.PLL5.div, value: '40'}
138+
- {id: CCM_ANALOG.PLL5.num, value: '0'}
139+
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
140+
sources:
141+
- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
142+
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
143+
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
144+
145+
/*******************************************************************************
146+
* Variables for BOARD_BootClockRUN configuration
147+
******************************************************************************/
148+
const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
149+
.loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
150+
};
151+
const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
152+
.loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
153+
.numerator = 0, /* 30 bit numerator of fractional loop divider */
154+
.denominator = 1, /* 30 bit denominator of fractional loop divider */
155+
};
156+
const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
157+
.loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
158+
};
159+
/*******************************************************************************
160+
* Code for BOARD_BootClockRUN configuration
161+
******************************************************************************/
66162
void BOARD_BootClockRUN(void)
67163
{
68-
/* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
69-
CLOCK_SetXtalFreq(24000000U);
164+
/* Init RTC OSC clock frequency. */
70165
CLOCK_SetRtcXtalFreq(32768U);
71-
72-
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
73-
CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
74-
75-
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
166+
/* Set XTAL 24MHz clock frequency. */
167+
CLOCK_SetXtalFreq(24000000U);
168+
/* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
169+
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
170+
CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
171+
/* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz. */
76172
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
77-
78-
CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
173+
/* Waiting for DCDC_STS_DC_OK bit is asserted */
174+
while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
175+
{
176+
}
177+
/* Init ARM PLL. */
178+
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
179+
/* Init System PLL. */
79180
#ifndef SKIP_SYSCLK_INIT
80-
CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
181+
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
81182
#endif
82-
#ifndef SKIP_USB_PLL_INIT
83-
CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
183+
/* Init Usb1 PLL. */
184+
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
185+
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
84186
#endif
85-
CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
86-
CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
87-
CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
88-
89-
CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
90-
CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
91-
92-
/* Disable unused clock */
93-
BOARD_BootClockGate();
94-
95-
/* Power down all unused PLL */
96-
CLOCK_DeinitAudioPll();
97-
CLOCK_DeinitVideoPll();
98-
CLOCK_DeinitEnetPll();
99-
CLOCK_DeinitUsb2Pll();
100-
101-
/* Configure UART divider to default */
102-
CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
103-
CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
104-
105-
/* Update core clock */
106-
SystemCoreClockUpdate();
187+
/* Enbale Audio PLL output. */
188+
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
189+
/* Enbale Video PLL output. */
190+
CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
191+
/* Enable ENET PLL output. */
192+
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
193+
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK;
194+
/* Set PERIPH_CLK2_PODF. */
195+
CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
196+
/* Set periph clock2 clock source. */
197+
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
198+
/* Set periph clock source. */
199+
CLOCK_SetMux(kCLOCK_PeriphMux, 0);
200+
/* Set AHB_PODF. */
201+
CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
202+
/* Set IPG_PODF. */
203+
CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
204+
/* Set ARM_PODF. */
205+
CLOCK_SetDiv(kCLOCK_ArmDiv, 1);
206+
/* Set preperiph clock source. */
207+
CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
208+
/* Set PERCLK_PODF. */
209+
CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
210+
/* Set per clock source. */
211+
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
212+
/* Set USDHC1_PODF. */
213+
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1);
214+
/* Set Usdhc1 clock source. */
215+
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
216+
/* Set USDHC2_PODF. */
217+
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
218+
/* Set Usdhc2 clock source. */
219+
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
220+
#ifndef SKIP_SYSCLK_INIT
221+
/* Set SEMC_PODF. */
222+
CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
223+
/* Set Semc alt clock source. */
224+
CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
225+
/* Set Semc clock source. */
226+
CLOCK_SetMux(kCLOCK_SemcMux, 0);
227+
#endif
228+
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
229+
/* Set FLEXSPI_PODF. */
230+
CLOCK_SetDiv(kCLOCK_FlexspiDiv, 1);
231+
/* Set Flexspi clock source. */
232+
CLOCK_SetMux(kCLOCK_FlexspiMux, 0);
233+
#endif
234+
/* Set CSI_PODF. */
235+
CLOCK_SetDiv(kCLOCK_CsiDiv, 1);
236+
/* Set Csi clock source. */
237+
CLOCK_SetMux(kCLOCK_CsiMux, 0);
238+
/* Set LPSPI_PODF. */
239+
CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
240+
/* Set Lpspi clock source. */
241+
CLOCK_SetMux(kCLOCK_LpspiMux, 2);
242+
/* Set TRACE_PODF. */
243+
CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
244+
/* Set Trace clock source. */
245+
CLOCK_SetMux(kCLOCK_TraceMux, 2);
246+
/* Set SAI1_CLK_PRED. */
247+
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
248+
/* Set SAI1_CLK_PODF. */
249+
CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
250+
/* Set Sai1 clock source. */
251+
CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
252+
/* Set SAI2_CLK_PRED. */
253+
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
254+
/* Set SAI2_CLK_PODF. */
255+
CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
256+
/* Set Sai2 clock source. */
257+
CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
258+
/* Set SAI3_CLK_PRED. */
259+
CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
260+
/* Set SAI3_CLK_PODF. */
261+
CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
262+
/* Set Sai3 clock source. */
263+
CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
264+
/* Set LPI2C_CLK_PODF. */
265+
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
266+
/* Set Lpi2c clock source. */
267+
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
268+
/* Set CAN_CLK_PODF. */
269+
CLOCK_SetDiv(kCLOCK_CanDiv, 1);
270+
/* Set Can clock source. */
271+
CLOCK_SetMux(kCLOCK_CanMux, 2);
272+
/* Set UART_CLK_PODF. */
273+
CLOCK_SetDiv(kCLOCK_UartDiv, 0);
274+
/* Set Uart clock source. */
275+
CLOCK_SetMux(kCLOCK_UartMux, 0);
276+
/* Set LCDIF_PRED. */
277+
CLOCK_SetDiv(kCLOCK_LcdifPreDiv, 1);
278+
/* Set LCDIF_CLK_PODF. */
279+
CLOCK_SetDiv(kCLOCK_LcdifDiv, 3);
280+
/* Set Lcdif pre clock source. */
281+
CLOCK_SetMux(kCLOCK_LcdifPreMux, 5);
282+
/* Set SPDIF0_CLK_PRED. */
283+
CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
284+
/* Set SPDIF0_CLK_PODF. */
285+
CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
286+
/* Set Spdif clock source. */
287+
CLOCK_SetMux(kCLOCK_SpdifMux, 3);
288+
/* Set FLEXIO1_CLK_PRED. */
289+
CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
290+
/* Set FLEXIO1_CLK_PODF. */
291+
CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
292+
/* Set Flexio1 clock source. */
293+
CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
294+
/* Set FLEXIO2_CLK_PRED. */
295+
CLOCK_SetDiv(kCLOCK_Flexio2PreDiv, 1);
296+
/* Set FLEXIO2_CLK_PODF. */
297+
CLOCK_SetDiv(kCLOCK_Flexio2Div, 7);
298+
/* Set Flexio2 clock source. */
299+
CLOCK_SetMux(kCLOCK_Flexio2Mux, 3);
300+
/* Set Pll3 sw clock source. */
301+
CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
302+
/* Set lvds1 clock source. */
303+
CCM_ANALOG->MISC1 =
304+
(CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
305+
/* Set SystemCoreClock variable. */
306+
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
107307
}

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