Added new features to TMPM3HQ

Author: Ganesh Ramachandran

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/crc_api.c

@@ -0,0 +1,79 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdbool.h>
+#include "crc_api.h"
+#include "device.h"
+
+#ifdef DEVICE_CRC
+
+static uint32_t final_xor;
+
+bool hal_crc_is_supported(const crc_mbed_config_t *config)
+{
+    if (config == NULL) {
+        return false;
+    }
+    // Currently supported only CRC16_CCITT polynomial.
+    if (config->polynomial != POLY_16BIT_CCITT) {
+        return false;
+    }
+
+    if (config->width != 16) {
+        return false;
+    }
+    // Not support for reflect_in and reflect_out.
+    if ((config->reflect_in == true) || (config->reflect_out == true)) {
+        return false;
+    }
+
+    return true;
+}
+
+void hal_crc_compute_partial_start(const crc_mbed_config_t *config)
+{
+    TSB_CG_FSYSENB_IPENB20 = 1;
+
+    // Intial Value as initial_xor
+    TSB_CRC->CLC = config->initial_xor;
+    final_xor = config->final_xor;
+
+    // Data width setting CRC data width is 8 bits.
+    // Form setting CRC form is CRC16.
+    TSB_CRC->TYP = 0x01;
+}
+
+void hal_crc_compute_partial(const uint8_t *data, const size_t size)
+{
+    if (data && size) {
+        uint32_t index = 0U;
+        for(index = 0U; index < size; index++) {
+            TSB_CRC->DIN = data[index];
+        }
+    }
+}
+
+uint32_t hal_crc_get_result(void)
+{
+    uint32_t result;
+
+    // Note: Please read [CRCCLC] twice and use the result of the 2nd time
+    result = TSB_CRC->CLC;
+    result = TSB_CRC->CLC ^ final_xor;
+
+    return (result);
+}
+#endif // DEVICE_CRC

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device.h

@@ -16,7 +16,8 @@
 #ifndef MBED_DEVICE_H
 #define MBED_DEVICE_H
 
-#define DEVICE_ID_LENGTH       32
+#define DEVICE_ID_LENGTH              32
+#define TRANSACTION_QUEUE_SIZE_SPI    4
 
 #include "objects.h"
 

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_ARM_STD/tmpm3hqfdfg.sct

@@ -40,9 +40,10 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE
 
   RW_IRAM1 0x200002D8 (0x10000 - 0x2D8 - Stack_Size)
   {
+    tmpm3hq_fc.o (+RO)
     .ANY (+RW, +ZI)
   }
 
-  ARM_LIB_STACK (0x200002D8+0x10000) EMPTY -Stack_Size { ; stack
+  ARM_LIB_STACK (0x20000000+0x10000) EMPTY -Stack_Size { ; stack
   }
 }

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_GCC_ARM/tmpm3hqfdfg.ld

@@ -109,7 +109,7 @@ SECTIONS
         __data_start__ = .;
         *(vtable)
         *(.data*)
-
+        *(.ram_func*)
         . = ALIGN(4);
         /* preinit data */
         PROVIDE_HIDDEN (__preinit_array_start = .);

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/device/TOOLCHAIN_IAR/tmpm3hqfdfg.icf

@@ -37,6 +37,15 @@ define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
 initialize by copy { readwrite };
 do not initialize  { section .noinit };
 
+initialize by copy { section RAMCODE };
+
+/* Place both in a block */
+define block RamCode { section RAMCODE };
+define block RamCodeInit { section RAMCODE_init };
+
+/* Place them in ROM and RAM */
+place in ROM_region { block RamCodeInit };
+place in RAM_region { block RamCode };
 place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region     { readonly };

targets/TARGET_TOSHIBA/TARGET_TMPM3HQ/flash_api.c

@@ -0,0 +1,130 @@
+/* mbed Microcontroller Library
+ * (C)Copyright TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION 2018 All rights reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "flash_api.h"
+#include "mbed_critical.h"
+#include "tmpm3hq_fc.h"
+
+#define PROGRAM_WRITE_MAX               (16U)           // Page program could be written 16 bytes/4 words once
+#define SECTOR_SIZE                     (0x8000)        // 32KB each sectors or block
+#define FLASH_CHIP_SIZE                 (0x00080000)    // Flash chip size is 512KByte
+#define MASK_CHIP_ID_FROM_ADD           (0x00FFFFFFUL)
+
+#define SUCCESS                         (0U)
+#define FAIL                            (-1)
+// IHOSC1EN
+#define CGOSCCR_IHOSC1EN_MASK           ((uint32_t)0x00000001)  // IHOSC1EN  :Mask
+#define CGOSCCR_IHOSC1EN_RW_DISABLE     ((uint32_t)0x00000000)  // IHOSC1EN  :[R/W] :Disable
+#define CGOSCCR_IHOSC1EN_RW_ENABLE      ((uint32_t)0x00000001)  // IHOSC1EN  :[R/W] :Enable
+
+static void internal_hosc_enable(void);
+
+int32_t flash_init(flash_t *obj)
+{
+    obj->flash_inited = 0;
+    obj->flash_inited = 1;
+    internal_hosc_enable();             // Internal HOSC enable
+    return 0;
+}
+
+int32_t flash_free(flash_t *obj)
+{
+    obj->flash_inited = 0;
+
+    return 0;
+}
+
+int32_t flash_erase_sector(flash_t *obj, uint32_t address)
+{
+    int status = FAIL;
+
+    if (obj->flash_inited == 0) {
+        flash_init(obj);
+    }
+
+    // We need to prevent flash accesses during erase operation
+    core_util_critical_section_enter();
+
+    if (TXZ_SUCCESS == fc_erase_block_code_flash((uint32_t*)FC_CODE_FLASH_ADDRESS_TOP, (uint32_t*)address)) {
+        status = SUCCESS;
+    } else {
+        // Do nothing
+    }
+
+    core_util_critical_section_exit();
+
+    return status;
+}
+
+int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
+{
+    int status = SUCCESS;
+
+    address &= MASK_CHIP_ID_FROM_ADD;
+
+    // We need to prevent flash accesses during program operation
+    core_util_critical_section_enter();
+
+    if (TXZ_SUCCESS == fc_write_code_flash((uint32_t*)data, (uint32_t*)address, size)) {
+        // Do nothing
+    } else {
+        status = FAIL;
+    }
+
+    core_util_critical_section_exit();
+
+    return status;
+}
+
+uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
+{
+    if ((address >= FC_CODE_FLASH_ADDRESS_TOP) && (address < (FC_CODE_FLASH_ADDRESS_TOP + FLASH_CHIP_SIZE))) {
+        return SECTOR_SIZE;
+    } else {
+        // Do nothing
+    }
+
+    return MBED_FLASH_INVALID_SIZE;
+}
+
+uint32_t flash_get_page_size(const flash_t *obj)
+{
+    return PROGRAM_WRITE_MAX;
+}
+
+uint32_t flash_get_start_address(const flash_t *obj)
+{
+    return FC_CODE_FLASH_ADDRESS_TOP;
+}
+
+uint32_t flash_get_size(const flash_t *obj)
+{
+    return FLASH_CHIP_SIZE;
+}
+
+static void internal_hosc_enable(void)
+{
+    uint32_t work;
+    work = (uint32_t)(TSB_CG->OSCCR & ~CGOSCCR_IHOSC1EN_MASK);
+    TSB_CG->OSCCR = (uint32_t)(work | CGOSCCR_IHOSC1EN_RW_ENABLE);
+}
+
+uint8_t flash_get_erase_value(const flash_t *obj)
+{
+    (void)obj;
+
+    return 0xFF;
+}