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jeromecoutantjeromecoutant
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STM32F1 : json clock source configuration
- default value is the same as before patch - system_stm32f1xx.c file is copied to family level with all other ST cube files - specific clock configuration is now in a new file: system_clock.c (target level)
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‎targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/system_clock.c

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/* mbed Microcontroller Library
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* Copyright (c) 2006-2017 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* This file configures the system clock as follows:
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*-----------------------------------------------------------------------------
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* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
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* | (external 8 MHz clock) | (internal 8 MHz)
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* | 2- PLL_HSE_XTAL |
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* | (external 8 MHz xtal) |
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* AHBCLK (MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* APB1CLK (MHz) | 36 | 32
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*-----------------------------------------------------------------------------
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* APB2CLK (MHz) | 72 | 64
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*-----------------------------------------------------------------------------
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* USB capable (48 MHz precise clock) | NO | NO
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*-----------------------------------------------------------------------------
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******************************************************************************
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*/
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#include "stm32f1xx.h"
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
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#define USE_PLL_HSE_EXTC (1) /* Use external clock */
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#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
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#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif
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uint8_t SetSysClock_PLL_HSI(void);
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/**
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* @brief Setup the microcontroller system
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* Initialize the Embedded Flash Interface, the PLL and update the
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* SystemCoreClock variable.
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* @note This function should be used only after reset.
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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{
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= 0x00000001U;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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#if !defined(STM32F105xC) && !defined(STM32F107xC)
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RCC->CFGR &= 0xF8FF0000U;
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#else
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RCC->CFGR &= 0xF0FF0000U;
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#endif /* STM32F105xC */
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= 0xFEF6FFFFU;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= 0xFF80FFFFU;
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#if defined(STM32F105xC) || defined(STM32F107xC)
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/* Reset PLL2ON and PLL3ON bits */
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RCC->CR &= 0xEBFFFFFFU;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x00FF0000U;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000U;
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#elif defined(STM32F100xB) || defined(STM32F100xE)
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000U;
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/* Reset CFGR2 register */
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RCC->CFGR2 = 0x00000000U;
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#else
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = 0x009F0000U;
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#endif /* STM32F105xC */
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#if defined(STM32F100xE) || defined(STM32F101xE) || defined(STM32F101xG) || defined(STM32F103xE) || defined(STM32F103xG)
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#ifdef DATA_IN_ExtSRAM
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SystemInit_ExtMemCtl();
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#endif /* DATA_IN_ExtSRAM */
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#endif
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
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#endif
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}
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function should be called only once the RCC clock configuration
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* is reset to the default reset state (done in SystemInit() function).
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* @param None
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* @retval None
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*/
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void SetSysClock(void)
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{
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/* 1- Try to start with HSE and external clock */
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#if USE_PLL_HSE_EXTC != 0
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if (SetSysClock_PLL_HSE(1) == 0)
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#endif
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{
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/* 2- If fail try to start with HSE and external xtal */
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#if USE_PLL_HSE_XTAL != 0
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if (SetSysClock_PLL_HSE(0) == 0)
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#endif
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{
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/* 3- If fail start with HSI clock */
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if (SetSysClock_PLL_HSI() == 0) {
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while(1) {
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// [TODO] Put something here to tell the user that a problem occured...
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}
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}
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}
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); // 72 MHz or 64 MHz
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}
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#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
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/******************************************************************************/
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/* PLL (clocked by HSE) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* Enable HSE oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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if (bypass == 0) {
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RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
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} else {
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RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
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}
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RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; // 72 MHz (8 MHz * 9)
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 72 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 72 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 36 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 72 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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return 0; // FAIL
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
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return 1; // OK
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}
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#endif
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/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
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uint8_t SetSysClock_PLL_HSI(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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/* Enable HSI oscillator and activate PLL with HSI as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSIState = RCC_HSI_ON;
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RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
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RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI_DIV2;
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RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
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if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
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return 0; // FAIL
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 64 MHz
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 64 MHz
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 32 MHz
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 64 MHz
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if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
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return 0; // FAIL
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}
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/* Output clock on MCO1 pin(PA8) for debugging purpose */
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//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 8 MHz
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return 1; // OK
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}
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