@@ -51,6 +51,34 @@ POSSIBILITY OF SUCH DAMAGE.
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#include <adi_tmr_config.h>
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#include <drivers/tmr/adi_tmr.h>
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+ /* Macro mapping from ADuCM4050 to ADuCM3029 */
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+ #if defined(__ADUCM3029__ )
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+ #define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
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+ #define PWM0CTL PWMCTL
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+ #define PWM0MATCH PWMMATCH
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+ #define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY
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+ #define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN
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+ #define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN
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+ #define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN
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+ #define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN
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+ #define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE
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+ #define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK
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+ #define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE
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+ #define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP
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+ #define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD
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+ #define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP
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+ #define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE
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+ #define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH
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+ #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
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+ #define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK
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+ #define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT
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+ #define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE
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+ #define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT
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+ #define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
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+ #define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD
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+ #endif /*__ADUCM3029__*/
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+
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+ #ifndef TARGET_Analog_Devices
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/* CTL register static configuration */
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static uint16_t aTimerCtlConfig [] =
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{
@@ -80,7 +108,7 @@ static uint16_t aTimerCtlConfig[] =
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(TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP ) |
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(TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN ) |
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(TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN ),
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-
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+ #if defined( __ADUCM4050__ )
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(TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP ) |
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(TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE ) |
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(TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE ) |
@@ -89,6 +117,7 @@ static uint16_t aTimerCtlConfig[] =
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(TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP ) |
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(TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN ) |
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(TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN ),
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+ #endif
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};
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/* LOAD register static configuration */
@@ -97,7 +126,9 @@ static uint16_t aTimerLoadConfig[] =
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TMR0_CFG_LOAD_VALUE ,
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TMR1_CFG_LOAD_VALUE ,
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TMR2_CFG_LOAD_VALUE ,
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+ #if defined(__ADUCM4050__ )
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TMR3_CFG_LOAD_VALUE ,
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+ #endif
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};
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/* Asynchronous LOAD static configuraton */
@@ -106,17 +137,21 @@ static uint16_t aTimerALoadConfig[] =
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TMR0_CFG_ASYNC_LOAD_VALUE ,
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TMR1_CFG_ASYNC_LOAD_VALUE ,
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TMR2_CFG_ASYNC_LOAD_VALUE ,
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+ #if defined(__ADUCM4050__ )
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TMR3_CFG_ASYNC_LOAD_VALUE ,
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+ #endif
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};
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/* EVENTSELECT static configuration */
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+ #if defined(__ADUCM4050__ )
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static uint16_t aTimerEventConfig [] =
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{
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TMR0_CFG_EVENT_CAPTURE ,
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TMR1_CFG_EVENT_CAPTURE ,
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TMR2_CFG_EVENT_CAPTURE ,
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TMR3_CFG_EVENT_CAPTURE ,
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};
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+ #endif
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/* PWM CTL static configuration */
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static uint16_t aTimerPwmCtlConfig [] =
@@ -129,7 +164,7 @@ static uint16_t aTimerPwmCtlConfig[] =
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(TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE ) |
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(TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH ),
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-
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+ #if defined( __ADUCM4050__ )
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(TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE ) |
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(TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH ),
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@@ -138,17 +173,20 @@ static uint16_t aTimerPwmCtlConfig[] =
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(TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE ) |
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(TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH ),
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+ #endif
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};
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/* PWM MATCH static configuration */
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static uint16_t aTimerPwmMatchConfig [] = {
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TMR0_CFG_PWM0_MATCH_VALUE ,
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TMR1_CFG_PWM0_MATCH_VALUE ,
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TMR2_CFG_PWM0_MATCH_VALUE ,
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+ #if defined(__ADUCM4050__ )
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TMR3_CFG_PWM0_MATCH_VALUE ,
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TMR3_CFG_PWM1_MATCH_VALUE ,
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TMR3_CFG_PWM2_MATCH_VALUE
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+ #endif
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};
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-
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+ #endif
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#endif /* ADI_TMR_DATA */
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