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Commit 6a7bfeb

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author
Edmund Hsu
committed
Disable unused Configuration data from compiler warning
Add __ADuCM3029__ constants
1 parent 20de336 commit 6a7bfeb

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1 file changed

+41
-3
lines changed
  • targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr

1 file changed

+41
-3
lines changed

targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/bsp/tmr/adi_tmr_data.c

Lines changed: 41 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,34 @@ POSSIBILITY OF SUCH DAMAGE.
5151
#include <adi_tmr_config.h>
5252
#include <drivers/tmr/adi_tmr.h>
5353

54+
/* Macro mapping from ADuCM4050 to ADuCM3029 */
55+
#if defined(__ADUCM3029__)
56+
#define BITM_TMR_RGB_CTL_EN BITM_TMR_CTL_EN
57+
#define PWM0CTL PWMCTL
58+
#define PWM0MATCH PWMMATCH
59+
#define BITM_TMR_RGB_STAT_BUSY BITM_TMR_STAT_BUSY
60+
#define BITM_TMR_RGB_CTL_EVTEN BITM_TMR_CTL_EVTEN
61+
#define BITM_TMR_RGB_CTL_RSTEN BITM_TMR_CTL_RSTEN
62+
#define BITP_TMR_RGB_CTL_RSTEN BITP_TMR_CTL_RSTEN
63+
#define BITP_TMR_RGB_CTL_EVTEN BITP_TMR_CTL_EVTEN
64+
#define BITP_TMR_RGB_CTL_PRE BITP_TMR_CTL_PRE
65+
#define BITP_TMR_RGB_CTL_CLK BITP_TMR_CTL_CLK
66+
#define BITP_TMR_RGB_CTL_MODE BITP_TMR_CTL_MODE
67+
#define BITP_TMR_RGB_CTL_UP BITP_TMR_CTL_UP
68+
#define BITP_TMR_RGB_CTL_RLD BITP_TMR_CTL_RLD
69+
#define BITP_TMR_RGB_CTL_SYNCBYP BITP_TMR_CTL_SYNCBYP
70+
#define BITP_TMR_RGB_PWM0CTL_IDLESTATE BITP_TMR_PWMCTL_IDLESTATE
71+
#define BITP_TMR_RGB_PWM0CTL_MATCH BITP_TMR_PWMCTL_MATCH
72+
#define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
73+
#define BITM_TMR_RGB_STAT_PDOK BITM_TMR_STAT_PDOK
74+
#define BITM_TMR_RGB_STAT_TIMEOUT BITM_TMR_STAT_TIMEOUT
75+
#define BITM_TMR_RGB_STAT_CAPTURE BITM_TMR_STAT_CAPTURE
76+
#define BITM_TMR_RGB_CLRINT_EVTCAPT BITM_TMR_CLRINT_EVTCAPT
77+
#define BITM_TMR_RGB_CLRINT_TIMEOUT BITM_TMR_CLRINT_TIMEOUT
78+
#define BITM_TMR_RGB_CTL_RLD BITM_TMR_CTL_RLD
79+
#endif /*__ADUCM3029__*/
80+
81+
#ifndef TARGET_Analog_Devices
5482
/* CTL register static configuration */
5583
static uint16_t aTimerCtlConfig[] =
5684
{
@@ -80,7 +108,7 @@ static uint16_t aTimerCtlConfig[] =
80108
(TMR2_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
81109
(TMR2_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
82110
(TMR2_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
83-
111+
#if defined(__ADUCM4050__)
84112
(TMR3_CFG_COUNT_UP << BITP_TMR_RGB_CTL_UP) |
85113
(TMR3_CFG_MODE << BITP_TMR_RGB_CTL_MODE) |
86114
(TMR3_CFG_PRESCALE_FACTOR << BITP_TMR_RGB_CTL_PRE) |
@@ -89,6 +117,7 @@ static uint16_t aTimerCtlConfig[] =
89117
(TMR3_CFG_ENABLE_SYNC_BYPASS << BITP_TMR_RGB_CTL_SYNCBYP) |
90118
(TMR3_CFG_ENABLE_PRESCALE_RESET << BITP_TMR_RGB_CTL_RSTEN) |
91119
(TMR3_CFG_ENABLE_EVENT_CAPTURE << BITP_TMR_RGB_CTL_EVTEN),
120+
#endif
92121
};
93122

94123
/* LOAD register static configuration */
@@ -97,7 +126,9 @@ static uint16_t aTimerLoadConfig[] =
97126
TMR0_CFG_LOAD_VALUE,
98127
TMR1_CFG_LOAD_VALUE,
99128
TMR2_CFG_LOAD_VALUE,
129+
#if defined(__ADUCM4050__)
100130
TMR3_CFG_LOAD_VALUE,
131+
#endif
101132
};
102133

103134
/* Asynchronous LOAD static configuraton */
@@ -106,17 +137,21 @@ static uint16_t aTimerALoadConfig[] =
106137
TMR0_CFG_ASYNC_LOAD_VALUE,
107138
TMR1_CFG_ASYNC_LOAD_VALUE,
108139
TMR2_CFG_ASYNC_LOAD_VALUE,
140+
#if defined(__ADUCM4050__)
109141
TMR3_CFG_ASYNC_LOAD_VALUE,
142+
#endif
110143
};
111144

112145
/* EVENTSELECT static configuration */
146+
#if defined(__ADUCM4050__)
113147
static uint16_t aTimerEventConfig[] =
114148
{
115149
TMR0_CFG_EVENT_CAPTURE,
116150
TMR1_CFG_EVENT_CAPTURE,
117151
TMR2_CFG_EVENT_CAPTURE,
118152
TMR3_CFG_EVENT_CAPTURE,
119153
};
154+
#endif
120155

121156
/* PWM CTL static configuration */
122157
static uint16_t aTimerPwmCtlConfig[] =
@@ -129,7 +164,7 @@ static uint16_t aTimerPwmCtlConfig[] =
129164

130165
(TMR2_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
131166
(TMR2_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
132-
167+
#if defined(__ADUCM4050__)
133168
(TMR3_CFG_PWM0_IDLE_STATE << BITP_TMR_RGB_PWM0CTL_IDLESTATE) |
134169
(TMR3_CFG_PWM0_MATCH_VALUE << BITP_TMR_RGB_PWM0CTL_MATCH),
135170

@@ -138,17 +173,20 @@ static uint16_t aTimerPwmCtlConfig[] =
138173

139174
(TMR3_CFG_PWM2_IDLE_STATE << BITP_TMR_RGB_PWM2CTL_IDLESTATE) |
140175
(TMR3_CFG_PWM2_MATCH_VALUE << BITP_TMR_RGB_PWM2CTL_MATCH),
176+
#endif
141177
};
142178

143179
/* PWM MATCH static configuration */
144180
static uint16_t aTimerPwmMatchConfig[] = {
145181
TMR0_CFG_PWM0_MATCH_VALUE,
146182
TMR1_CFG_PWM0_MATCH_VALUE,
147183
TMR2_CFG_PWM0_MATCH_VALUE,
184+
#if defined(__ADUCM4050__)
148185
TMR3_CFG_PWM0_MATCH_VALUE,
149186
TMR3_CFG_PWM1_MATCH_VALUE,
150187
TMR3_CFG_PWM2_MATCH_VALUE
188+
#endif
151189
};
152-
190+
#endif
153191

154192
#endif /* ADI_TMR_DATA */

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