[M2351] Support configurable for partitioning flash/SRAM

Author: ccli8

targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct

@@ -1,25 +1,66 @@
 #! armcc -E
 
-#include "partition_M2351_sub.h"
+/* Default flash/SRAM partition
+ *
+ * Default flash partition:
+ *   Secure:        256KiB
+ *   Non-secure:    256KiB
+ * 
+ * Default SRAM partition:
+ *   Secure:        32KiB
+ *   Non-secure:    64KiB
+ */
+#if defined(__DOMAIN_NS) && __DOMAIN_NS
+
+#ifndef MBED_APP_START
+#define MBED_APP_START      0x10040000
+#endif
+
+#ifndef MBED_APP_SIZE
+#define MBED_APP_SIZE       0x40000
+#endif
+
+#ifndef MBED_RAM_START
+#define MBED_RAM_START      0x30008000
+#endif
+
+#ifndef MBED_RAM_SIZE
+#define MBED_RAM_SIZE       0x10000
+#endif
+
+#else
 
-/* Check relevant macros have been defined */
-#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
-#error("NU_TZ_SECURE_FLASH_SIZE not defined")
+#ifndef MBED_APP_START
+#define MBED_APP_START      0x0
 #endif
-#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
-#error("NU_TZ_SECURE_SRAM_SIZE not defined")
+
+#ifndef MBED_APP_SIZE
+#define MBED_APP_SIZE       0x40000
 #endif
-#if (! defined(NU_TZ_NSC_REGION_SIZE))
-#error("NU_TZ_NSC_REGION_SIZE not defined")
+
+#ifndef MBED_RAM_START
+#define MBED_RAM_START      0x20000000
+#endif
+
+#ifndef MBED_RAM_SIZE
+#define MBED_RAM_SIZE       0x8000
+#endif
+
 #endif
 
 /* Requirements for NSC location
  *
  * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
  * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
- * 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
+ * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
+ * 4. NSC region size defaults to 4KiB if not defined.
  */
-#define NU_TZ_NSC_REGION_BASE       (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
+#ifndef NU_TZ_NSC_START
+#define NU_TZ_NSC_START         (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
+#endif
+#ifndef NU_TZ_NSC_SIZE
+#define NU_TZ_NSC_SIZE          0x1000
+#endif
 
 /* Initial/ISR stack size */
 #if (! defined(NU_INITIAL_STACK_SIZE))
@@ -32,14 +73,6 @@
 
 #if defined(__DOMAIN_NS) && __DOMAIN_NS
 
-#if (! defined(MBED_APP_START))
-#define MBED_APP_START              (0x10000000 + NU_TZ_SECURE_FLASH_SIZE)
-#endif
-
-#if (! defined(MBED_APP_SIZE))
-#define MBED_APP_SIZE               (0x80000 - NU_TZ_SECURE_FLASH_SIZE)
-#endif
-
 LR_IROM1    MBED_APP_START
 {
     /* load address = execution address */
@@ -50,7 +83,7 @@ LR_IROM1    MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   NU_INITIAL_STACK_SIZE
+    ARM_LIB_STACK   MBED_RAM_START  EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
@@ -68,24 +101,16 @@ LR_IROM1    MBED_APP_START
         .ANY (+RW +ZI)
     }
 
-    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16))
+    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
     {
     }
 }
 
 ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000)
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE)
 
 #else
 
-#if (! defined(MBED_APP_START))
-#define MBED_APP_START              0
-#endif
-
-#if (! defined(MBED_APP_SIZE))
-#define MBED_APP_SIZE               NU_TZ_SECURE_FLASH_SIZE
-#endif
-
 LR_IROM1 MBED_APP_START
 {
     /* load address = execution address */
@@ -114,23 +139,27 @@ LR_IROM1 MBED_APP_START
         .ANY (+RW +ZI)
     }
 
-    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
+    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
     {
     }
 }
 
-LR_IROM2 NU_TZ_NSC_REGION_BASE
+LR_IROM_NSC NU_TZ_NSC_START             NU_TZ_NSC_SIZE
 {
-    NSC_ROM +0  NU_TZ_NSC_REGION_SIZE  
+    ER_IROM_NSC +0  
     {
         *(Veneer$$CMSE)
     }
+    
+    ER_IROM_NSC_PAD +0  FILL    0xFFFFFFFF  (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
+    {
+    }
 }
 
-ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE)
-ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE))
+ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
+ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
 /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
-ScatterAssert(LoadBase(LR_IROM2) >= 0x4000)
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE))
+ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE))
 
 #endif

targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/partition_M2351_sub.h

@@ -1,25 +1,66 @@
 #! armcc -E
 
-#include "partition_M2351_sub.h"
+/* Default flash/SRAM partition
+ *
+ * Default flash partition:
+ *   Secure:        256KiB
+ *   Non-secure:    256KiB
+ * 
+ * Default SRAM partition:
+ *   Secure:        32KiB
+ *   Non-secure:    64KiB
+ */
+#if defined(__DOMAIN_NS) && __DOMAIN_NS
+
+#ifndef MBED_APP_START
+#define MBED_APP_START      0x10040000
+#endif
+
+#ifndef MBED_APP_SIZE
+#define MBED_APP_SIZE       0x40000
+#endif
+
+#ifndef MBED_RAM_START
+#define MBED_RAM_START      0x30008000
+#endif
+
+#ifndef MBED_RAM_SIZE
+#define MBED_RAM_SIZE       0x10000
+#endif
+
+#else
 
-/* Check relevant macros have been defined */
-#if (! defined(NU_TZ_SECURE_FLASH_SIZE))
-#error("NU_TZ_SECURE_FLASH_SIZE not defined")
+#ifndef MBED_APP_START
+#define MBED_APP_START      0x0
 #endif
-#if (! defined(NU_TZ_SECURE_SRAM_SIZE))
-#error("NU_TZ_SECURE_SRAM_SIZE not defined")
+
+#ifndef MBED_APP_SIZE
+#define MBED_APP_SIZE       0x40000
 #endif
-#if (! defined(NU_TZ_NSC_REGION_SIZE))
-#error("NU_TZ_NSC_REGION_SIZE not defined")
+
+#ifndef MBED_RAM_START
+#define MBED_RAM_START      0x20000000
+#endif
+
+#ifndef MBED_RAM_SIZE
+#define MBED_RAM_SIZE       0x8000
+#endif
+
 #endif
 
 /* Requirements for NSC location
  *
  * 1. By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000.
  * 2. Greentea flash IAP uses last 4 sectors for its test. Avoid this range.
- * 3. Greentea NVSTORE uses last 2 sectors or 4KB x 2 for its test. Avoid this range.
+ * 3. Greentea NVSTORE uses last 2 sectors or 4KiB x 2 for its test. Avoid this range.
+ * 4. NSC region size defaults to 4KiB if not defined.
  */
-#define NU_TZ_NSC_REGION_BASE       (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
+#ifndef NU_TZ_NSC_START
+#define NU_TZ_NSC_START         (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_SIZE)
+#endif
+#ifndef NU_TZ_NSC_SIZE
+#define NU_TZ_NSC_SIZE          0x1000
+#endif
 
 /* Initial/ISR stack size */
 #if (! defined(NU_INITIAL_STACK_SIZE))
@@ -32,14 +73,6 @@
 
 #if defined(__DOMAIN_NS) && __DOMAIN_NS
 
-#if (! defined(MBED_APP_START))
-#define MBED_APP_START              (0x10000000 + NU_TZ_SECURE_FLASH_SIZE)
-#endif
-
-#if (! defined(MBED_APP_SIZE))
-#define MBED_APP_SIZE               (0x80000 - NU_TZ_SECURE_FLASH_SIZE)
-#endif
-
 LR_IROM1    MBED_APP_START
 {
     /* load address = execution address */
@@ -50,7 +83,7 @@ LR_IROM1    MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   NU_INITIAL_STACK_SIZE
+    ARM_LIB_STACK   MBED_RAM_START  EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
@@ -68,24 +101,16 @@ LR_IROM1    MBED_APP_START
         .ANY (+RW +ZI)
     }
 
-    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (0x30018000 - AlignExpr(ImageLimit(RW_IRAM1), 16))
+    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
     {
     }
 }
 
 ScatterAssert(LoadLimit(LR_IROM1) <= (MBED_APP_START + MBED_APP_SIZE))
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x30018000)
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= MBED_RAM_START + MBED_RAM_SIZE)
 
 #else
 
-#if (! defined(MBED_APP_START))
-#define MBED_APP_START              0
-#endif
-
-#if (! defined(MBED_APP_SIZE))
-#define MBED_APP_SIZE               NU_TZ_SECURE_FLASH_SIZE
-#endif
-
 LR_IROM1 MBED_APP_START
 {
     /* load address = execution address */
@@ -114,23 +139,27 @@ LR_IROM1 MBED_APP_START
         .ANY (+RW +ZI)
     }
 
-    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (0x20000000 + NU_TZ_SECURE_SRAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
+    ARM_LIB_HEAP    AlignExpr(+0, 16) EMPTY (MBED_RAM_START + MBED_RAM_SIZE - AlignExpr(ImageLimit(RW_IRAM1), 16))
     {
     }
 }
 
-LR_IROM2 NU_TZ_NSC_REGION_BASE
+LR_IROM_NSC NU_TZ_NSC_START             NU_TZ_NSC_SIZE
 {
-    NSC_ROM +0  NU_TZ_NSC_REGION_SIZE  
+    ER_IROM_NSC +0  
     {
         *(Veneer$$CMSE)
     }
+    
+    ER_IROM_NSC_PAD +0  FILL    0xFFFFFFFF  (NU_TZ_NSC_START + NU_TZ_NSC_SIZE - ImageLimit(ER_IROM_NSC))
+    {
+    }
 }
 
-ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_REGION_BASE)
-ScatterAssert(LoadLimit(LR_IROM2) <= (NU_TZ_NSC_REGION_BASE + NU_TZ_NSC_REGION_SIZE))
+ScatterAssert(LoadLimit(LR_IROM1) <= NU_TZ_NSC_START)
+ScatterAssert(LoadLimit(LR_IROM_NSC) <= (NU_TZ_NSC_START + NU_TZ_NSC_SIZE))
 /* By IDAU, 0~0x4000 is secure. NSC can only locate in 0x4000~0x10000000 */
-ScatterAssert(LoadBase(LR_IROM2) >= 0x4000)
-ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (0x20000000 + NU_TZ_SECURE_SRAM_SIZE))
+ScatterAssert(LoadBase(LR_IROM_NSC) >= 0x4000)
+ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_START + MBED_RAM_SIZE))
 
 #endif