@@ -89,10 +89,16 @@ void mbed_start_application(uintptr_t address)
89
89
90
90
static void powerdown_nvic ()
91
91
{
92
- int isr_groups_32 ;
93
92
int i ;
93
+ #if defined(__CORTEX_M0PLUS )
94
+ NVIC -> ICER [0 ] = 0xFFFFFFFF ;
95
+ NVIC -> ICPR [0 ] = 0xFFFFFFFF ;
96
+ for (i = 0 ; i < 8 ; i ++ ) {
97
+ NVIC -> IP [i ] = 0x00000000 ;
98
+ }
99
+ #else
94
100
int j ;
95
-
101
+ int isr_groups_32 ;
96
102
#if defined(__CORTEX_M23 )
97
103
// M23 doesn't support ICTR and supports up to 240 external interrupts.
98
104
isr_groups_32 = 8 ;
@@ -110,6 +116,7 @@ static void powerdown_nvic()
110
116
#endif
111
117
}
112
118
}
119
+ #endif
113
120
}
114
121
115
122
static void powerdown_scb (uint32_t vtor )
@@ -122,21 +129,21 @@ static void powerdown_scb(uint32_t vtor)
122
129
SCB -> AIRCR = 0x05FA | 0x0000 ;
123
130
SCB -> SCR = 0x00000000 ;
124
131
// SCB->CCR - Implementation defined value
125
- #if defined(__CORTEX_M23 )
126
- for (i = 0 ; i < 2 ; i ++ ) {
127
- SCB -> SHPR [i ] = 0x00 ;
128
- }
132
+ int num_pri_reg ; // Number of priority registers
133
+ #if defined(__CORTEX_M0PLUS ) || defined(__CORTEX_M23 )
134
+ num_pri_reg = 2 ;
129
135
#else
130
- for (i = 0 ; i < 12 ; i ++ ) {
131
- #if defined(__CORTEX_M7 )
136
+ num_pri_reg = 12 ;
137
+ #endif
138
+ for (i = 0 ; i < num_pri_reg ; i ++ ) {
139
+ #if defined(__CORTEX_M7 ) || defined(__CORTEX_M23 )
132
140
SCB -> SHPR [i ] = 0x00 ;
133
141
#else
134
142
SCB -> SHP [i ] = 0x00 ;
135
143
#endif
136
144
}
137
- #endif
138
145
SCB -> SHCSR = 0x00000000 ;
139
- #if defined(__CORTEX_M23 )
146
+ #if defined(__CORTEX_M23 ) || defined( __CORTEX_M0PLUS )
140
147
#else
141
148
SCB -> CFSR = 0xFFFFFFFF ;
142
149
SCB -> HFSR = SCB_HFSR_DEBUGEVT_Msk | SCB_HFSR_FORCED_Msk | SCB_HFSR_VECTTBL_Msk ;
@@ -170,7 +177,11 @@ __asm static void start_new_application(void *sp, void *pc)
170
177
void start_new_application (void * sp , void * pc )
171
178
{
172
179
__asm volatile (
173
- "movw r2, #0 \n" // Fail to compile "mov r2, #0" with ARMC6. Replace with MOVW.
180
+ #if defined(__CORTEX_M0PLUS )
181
+ "mov r2 , #0 \n " // No MOVW instruction on Cortex-M0+
182
+ #else
183
+ "movw r2 , #0 \n " // Fail to compile "mov r2, #0" with ARMC6. Replace with MOVW.
184
+ #endif
174
185
// We needn't "movt r2, #0" immediately following because MOVW
175
186
// will zero-extend the 16-bit immediate.
176
187
"msr control, r2 \n" // Switch to main stack
0 commit comments