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jeromecoutantjeromecoutant
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STM32U5 : STM32U5xxxxx sub-families
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9 files changed

+538
-6
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9 files changed

+538
-6
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‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/CMakeLists.txt

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@@ -19,6 +19,7 @@ target_include_directories(mbed-stm32u575xg
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target_sources(mbed-stm32u575xg
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INTERFACE
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${STARTUP_FILE}
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system_clock.c
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)
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mbed_set_linker_script(mbed-stm32u575xg ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/cmsis_nvic.h

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@@ -22,15 +22,15 @@
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#endif
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#if !defined(MBED_ROM_SIZE)
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#define MBED_ROM_SIZE 0x0 // 0 B
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#define MBED_ROM_SIZE 0x100000 // 1 MB
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#endif
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#if !defined(MBED_RAM_START)
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#define MBED_RAM_START 0x20000000
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#endif
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#if !defined(MBED_RAM_SIZE)
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#define MBED_RAM_SIZE 0x0 // 0 B
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#define MBED_RAM_SIZE 0xC0000 // 768 KB
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#endif
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#define NVIC_NUM_VECTORS 141

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xG/system_clock.c

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@@ -0,0 +1,175 @@
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/* mbed Microcontroller Library
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* SPDX-License-Identifier: BSD-3-Clause
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******************************************************************************
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*
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* Copyright (c) 2015-2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/**
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* This file configures the system clock depending on config from targets.json:
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*-----------------------------------------------------------------------------
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* System clock source | 1- USE_PLL_HSE_EXTC (external clock)
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* | 2- USE_PLL_HSE_XTAL (external xtal)
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* | 3- USE_PLL_HSI (internal 16 MHz)
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* | 4- USE_PLL_MSI (internal 100kHz to 48 MHz)
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*-----------------------------------------------------------------------------
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* SYSCLK(MHz) | 160
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* AHBCLK (MHz) | 160
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* APB1CLK (MHz) | 160
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* APB2CLK (MHz) | 160
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* APB3CLK (MHz) | 160
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* USB capable | TODO
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*-----------------------------------------------------------------------------
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**/
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33+
#include "stm32u5xx.h"
34+
#include "mbed_error.h"
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// clock source is selected with CLOCK_SOURCE in json config
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#define USE_PLL_HSE_EXTC 0x8 // Use external clock (OSC_IN)
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#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (OSC_IN/OSC_OUT)
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#define USE_PLL_HSI 0x2 // Use HSI internal clock
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#define USE_PLL_MSI 0x1 // Use MSI internal clock
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42+
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
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uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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#if ((CLOCK_SOURCE) & USE_PLL_HSI)
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uint8_t SetSysClock_PLL_HSI(void);
48+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
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#if ((CLOCK_SOURCE) & USE_PLL_MSI)
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uint8_t SetSysClock_PLL_MSI(void);
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#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */
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/**
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* @brief Configures the System clock source, PLL Multiplier and Divider factors,
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* AHB/APBx prescalers and Flash settings
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* @note This function is called in mbed_sdk_init() function (targets/TARGET_STM/mbed_overrides.c)
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* and after each deepsleep period in hal_deepsleep() (targets/TARGET_STM/sleep.c)
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* @param None
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* @retval None
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*/
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64+
MBED_WEAK void SetSysClock(void)
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{
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#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
67+
/* 1- Try to start with HSE and external clock */
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if (SetSysClock_PLL_HSE(1) == 0)
69+
#endif
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{
71+
#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
72+
/* 2- If fail try to start with HSE and external xtal */
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if (SetSysClock_PLL_HSE(0) == 0)
74+
#endif
75+
{
76+
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
77+
/* 3- If fail start with HSI clock */
78+
if (SetSysClock_PLL_HSI() == 0)
79+
#endif
80+
{
81+
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
82+
/* 4- If fail start with MSI clock */
83+
if (SetSysClock_PLL_MSI() == 0)
84+
#endif
85+
{
86+
{
87+
error("SetSysClock failed\n");
88+
}
89+
}
90+
}
91+
}
92+
}
93+
}
94+
95+
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
96+
/******************************************************************************/
97+
/* PLL (clocked by HSE) used as System clock source */
98+
/******************************************************************************/
99+
MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
100+
{
101+
return 0;
102+
}
103+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
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105+
#if ((CLOCK_SOURCE) & USE_PLL_HSI)
106+
/******************************************************************************/
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/* PLL (clocked by HSI) used as System clock source */
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/******************************************************************************/
109+
uint8_t SetSysClock_PLL_HSI(void)
110+
{
111+
return 0; // TODO
112+
}
113+
#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
114+
115+
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
116+
/******************************************************************************/
117+
/* PLL (clocked by MSI) used as System clock source */
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/******************************************************************************/
119+
MBED_WEAK uint8_t SetSysClock_PLL_MSI(void)
120+
{
121+
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
122+
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
123+
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
124+
125+
__HAL_RCC_PWR_CLK_ENABLE();
126+
HAL_PWREx_DisableUCPDDeadBattery(); /* Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral */
127+
HAL_PWREx_EnableVddA();
128+
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
129+
130+
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
131+
| RCC_OSCILLATORTYPE_MSI;
132+
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
133+
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
134+
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
135+
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
136+
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
137+
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_0;
138+
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
139+
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
140+
RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV4;
141+
RCC_OscInitStruct.PLL.PLLM = 3;
142+
RCC_OscInitStruct.PLL.PLLN = 10;
143+
RCC_OscInitStruct.PLL.PLLP = 2;
144+
RCC_OscInitStruct.PLL.PLLQ = 2;
145+
RCC_OscInitStruct.PLL.PLLR = 1;
146+
RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_1;
147+
RCC_OscInitStruct.PLL.PLLFRACN = 0;
148+
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
149+
return 0; // FAIL
150+
}
151+
152+
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
153+
| RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
154+
| RCC_CLOCKTYPE_PCLK3;
155+
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
156+
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
157+
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
158+
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
159+
RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
160+
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
161+
return 0; // FAIL
162+
}
163+
164+
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RNG;
165+
PeriphClkInit.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
166+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) {
167+
return 0; // FAIL
168+
}
169+
170+
HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY);
171+
HAL_ICACHE_Enable();
172+
173+
return 1; // OK
174+
}
175+
#endif /* ((CLOCK_SOURCE) & USE_PLL_MSI) */

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/CMakeLists.txt

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@@ -1,6 +1,8 @@
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# Copyright (c) 2020 ARM Limited. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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4+
add_subdirectory(TARGET_NUCLEO_U575ZI_Q EXCLUDE_FROM_ALL)
5+
46
if(${MBED_TOOLCHAIN} STREQUAL "GCC_ARM")
57
set(STARTUP_FILE TOOLCHAIN_GCC_ARM/startup_stm32u575xx.S)
68
set(LINKER_FILE TOOLCHAIN_GCC_ARM/stm32u575xi.ld)
@@ -19,6 +21,7 @@ target_include_directories(mbed-stm32u575xi
1921
target_sources(mbed-stm32u575xi
2022
INTERFACE
2123
${STARTUP_FILE}
24+
system_clock.c
2225
)
2326

2427
mbed_set_linker_script(mbed-stm32u575xi ${CMAKE_CURRENT_SOURCE_DIR}/${LINKER_FILE})

‎targets/TARGET_STM/TARGET_STM32U5/TARGET_STM32U575xI/cmsis_nvic.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -22,15 +22,15 @@
2222
#endif
2323

2424
#if !defined(MBED_ROM_SIZE)
25-
#define MBED_ROM_SIZE 0x0 // 0 B
25+
#define MBED_ROM_SIZE 0x200000 // 2 MB
2626
#endif
2727

2828
#if !defined(MBED_RAM_START)
2929
#define MBED_RAM_START 0x20000000
3030
#endif
3131

3232
#if !defined(MBED_RAM_SIZE)
33-
#define MBED_RAM_SIZE 0x0 // 0 B
33+
#define MBED_RAM_SIZE 0xC0000 // 768 KB
3434
#endif
3535

3636
#define NVIC_NUM_VECTORS 141

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