M2354: Update to BSP v3.00.001

1.  Change to support MP chip. Original M2355 BSP is for test chip.
2.  UART0, used for USB VCOM, has change in clock enable bit. So chip/board version and BSP version must match.
3.  Remove TF-M legacy code.

Author: ccli8

targets/TARGET_NUVOTON/TARGET_M2354/PeripheralPins.c

@@ -246,6 +246,7 @@ const PinMap PinMap_UART_RX[] = {
     {PA_2, UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
     {NU_PINNAME_BIND(PA_2, UART_4), UART_4, SYS_GPA_MFPL_PA2MFP_UART4_RXD},
 #endif
+    {PA_4, UART_0, SYS_GPA_MFPL_PA4MFP_UART0_RXD},
     {PA_4, UART_5, SYS_GPA_MFPL_PA4MFP_UART5_RXD},
     {PA_6, UART_0, SYS_GPA_MFPL_PA6MFP_UART0_RXD},
     {PA_8, UART_1, SYS_GPA_MFPH_PA8MFP_UART1_RXD},
@@ -508,7 +509,6 @@ const PinMap PinMap_SD_CLK[] = {
 
 const PinMap PinMap_SD_CD[] = {
     {PB_12, SD_0, SYS_GPB_MFPH_PB12MFP_SD0_nCD},
-    {PD_13, SD_0, SYS_GPD_MFPH_PD13MFP_SD0_nCD},
 
     {NC,    NC,    0}
 };

targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_NS/device/TOOLCHAIN_ARMC6/M2354.sct

@@ -42,7 +42,7 @@ LR_IROM1    MBED_APP_START
      *
      * Vector table base address is required to be 128-byte aligned at a minimum.
      * A PE might impose further restrictions on it. */
-    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 114))
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 116))
     {
     }
 

targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_NS/device/TOOLCHAIN_GCC_ARM/M2354.ld

@@ -38,7 +38,7 @@ MEMORY
 /**
  * Must match cmsis_nvic.h
  */
-__vector_size = 4 * (16 + 114);
+__vector_size = 4 * (16 + 116);
 
 
 /* Linker script to place sections and symbol values. Should be used together

targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_NS/device/TOOLCHAIN_IAR/M2354.icf

@@ -36,7 +36,7 @@ define symbol __ICFEDIT_region_IRAM_end__       = MBED_RAM_APP_START + MBED_RAM_
 
 /*-Sizes-*/
 define symbol __ICFEDIT_size_cstack__           = MBED_BOOT_STACK_SIZE;
-define symbol __ICFEDIT_size_intvec__           = 4 * (16 + 114);
+define symbol __ICFEDIT_size_intvec__           = 4 * (16 + 116);
 define symbol __ICFEDIT_size_heap__             = 0x400;
 
 /**** End of ICF editor section. ###ICF###*/

targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_S/device/TOOLCHAIN_ARMC6/M2354.sct

@@ -39,48 +39,19 @@ LR_IROM1 MBED_APP_START
      * Secure non-PSA/Non-secure non-PSA/Non-secure PSA requires just one boot stack (MSP).
      * Secure PSA(TFM) requires two boot stacks (MSP/PSP).
      */
-#if TFM_LVL == 0
 
     ARM_LIB_STACK   MBED_RAM_APP_START  EMPTY   MBED_BOOT_STACK_SIZE
     {
     }
 
-#else
-
-    /* Stack Pointer (SP) configuration with ARM/ARMC6
-     *
-     * SP would go through the following configuration sequence:
-     * (1)  SP(MSP) <- Entry 0 of vector table (on H/W reset)
-     * (2)  Switch SP from MSP to PSP in startup file (as TFM requests)
-     * (3.1)    SP(PSP) <- ARM_LIB_STACK (C/C++ runtime initialization)
-     * (3.2)    SP(PSP) reconfigured in __user_setup_stackheap()
-     *
-     * S(3.1) or S(3.2) may cause SP(PSP) incorrectly configured. We name ARM_LIB_STACK for
-     * PSP stack rather than MSP stack to get around this error. MSP stack is named separately
-     * with ARM_LIB_STACK_MSP.
-     */
-
-    #warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
-    ARM_LIB_STACK_MSP   MBED_RAM_APP_START  EMPTY   0x800
-    {
-    }
-
-    ARM_LIB_STACK       AlignExpr(+0, 32)   EMPTY   0x800
-    {
-    }
-
-#endif
-
     /* Reserve for vectors
      *
      * Vector table base address is required to be 128-byte aligned at a minimum.
      * A PE might impose further restrictions on it. */
-    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 114))
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 116))
     {
     }
 
-#if TFM_LVL == 0
-
     /* 16 byte-aligned */
     RW_IRAM1                AlignExpr(+0, 16)
     {
@@ -91,32 +62,6 @@ LR_IROM1 MBED_APP_START
     {
     }
 
-#elif TFM_LVL == 1
-
-    TFM_SECURE_STACK        AlignExpr(+0, 128)  EMPTY   0x1000
-    {
-    }
-
-    TFM_UNPRIV_SCRATCH      AlignExpr(+0, 32)   EMPTY   0x400
-    {
-    }
-
-    /* 16 byte-aligned */
-    ER_TFM_DATA             AlignExpr(+0, 16)
-    {
-        .ANY (+RW +ZI)
-    }
-
-    ARM_LIB_HEAP            AlignExpr(+0, 16)   EMPTY (MBED_RAM_APP_START + MBED_RAM_APP_SIZE - AlignExpr(ImageLimit(ER_TFM_DATA), 16))
-    {
-    }
-
-#elif TFM_LVL > 1
-
-#error("TFM level 2/3 are not supported yet")
-    
-#endif
-
 }
 
 LR_IROM_NSC NU_TZ_NSC_START     NU_TZ_NSC_SIZE
@@ -132,8 +77,3 @@ ScatterAssert(ImageBase(ER_IROM_NSC) >= 0x800)
 
 /* Heap must be allocated in RAM. */
 ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= (MBED_RAM_APP_START + MBED_RAM_APP_SIZE))
-
-#if (TFM_LVL > 0)
-/* Application ROM code cannot overlap with TDB internal storage area. */
-ScatterAssert(LoadLimit(LR_IROM1) <= NU_TDB_INTERNAL_STORAGE_START)
-#endif

targets/TARGET_NUVOTON/TARGET_M2354/TARGET_M23_S/device/TOOLCHAIN_GCC_ARM/M2354.ld

@@ -26,18 +26,8 @@
 #define MBED_BOOT_STACK_SIZE    0x400
 #endif
 
-#if (TFM_LVL == 0)
-
 StackSize = MBED_BOOT_STACK_SIZE;
 
-#else
-
-#warning("Ignore MBED_BOOT_STACK_SIZE in Secure PSA build")
-__msp_stack_size__ = 0x00000800;
-__psp_stack_size__ = 0x00000800;
-
-#endif
-
 MEMORY
 {
   VECTORS (rx)          : ORIGIN = MBED_APP_START,          LENGTH = 0x00000400
@@ -49,7 +39,7 @@ MEMORY
 /**
  * Must match cmsis_nvic.h
  */
-__vector_size = 4 * (16 + 114);
+__vector_size = 4 * (16 + 116);
 
 
 /* Linker script to place sections and symbol values. Should be used together
@@ -89,8 +79,6 @@ SECTIONS
          . = ALIGN(8);
     } > VECTORS
 
-#if (TFM_LVL == 0)
-
     .copy.table : ALIGN(4)
     {
         __copy_table_start__ = .;
@@ -108,35 +96,6 @@ SECTIONS
         __zero_table_end__ = .;
     } > FLASH
 
-#elif (TFM_LVL == 1)
-
-    .copy.table : ALIGN(4)
-    {
-        __copy_table_start__ = .;
-        LONG (LOADADDR(.TFM_DATA))
-        LONG (ADDR(.TFM_DATA))
-        LONG (SIZEOF(.TFM_DATA))
-        __copy_table_end__ = .;
-    } > FLASH
-
-    .zero.table : ALIGN(4)
-    {
-        __zero_table_start__ = .;
-        LONG (ADDR(.TFM_BSS))
-        LONG (SIZEOF(.TFM_BSS))
-        LONG (ADDR(.TFM_SECURE_STACK))
-        LONG (SIZEOF(.TFM_SECURE_STACK))
-        LONG (ADDR(.TFM_UNPRIV_SCRATCH))
-        LONG (SIZEOF(.TFM_UNPRIV_SCRATCH))
-        __zero_table_end__ = .;
-    } > FLASH
-
-#else
-
-    #error("TFM level 2/3 are not supported yet")
-    
-#endif
-
     .text :
     {
         *(.text*)
@@ -174,8 +133,6 @@ SECTIONS
      * is assigned conditionally according to Secure PSA or not.
      */
 
-#if (TFM_LVL == 0)
-
     .stack (NOLOAD) :
     {
         . = ALIGN(8);
@@ -186,54 +143,6 @@ SECTIONS
 
     PROVIDE(__stack = __StackTop);
 
-#else
-
-    .msp_stack (NOLOAD) :
-    {
-        . = ALIGN(32);
-        . += __msp_stack_size__;
-    } > RAM_INTERN
-    Image$$ARM_LIB_STACK_MSP$$ZI$$Base = ADDR(.msp_stack);
-    Image$$ARM_LIB_STACK_MSP$$ZI$$Limit = ADDR(.msp_stack) + SIZEOF(.msp_stack);
-    __StackLimit = Image$$ARM_LIB_STACK_MSP$$ZI$$Base;
-    __StackTop = Image$$ARM_LIB_STACK_MSP$$ZI$$Limit;
-
-    .psp_stack (NOLOAD) :
-    {
-        . = ALIGN(32);
-        . += __psp_stack_size__;
-    } > RAM_INTERN
-    Image$$ARM_LIB_STACK$$ZI$$Base = ADDR(.psp_stack);
-    Image$$ARM_LIB_STACK$$ZI$$Limit = ADDR(.psp_stack) + SIZEOF(.psp_stack);
-
-    PROVIDE(__stack = Image$$ARM_LIB_STACK$$ZI$$Limit);
-
-#endif
-
-#if (TFM_LVL == 1)
-
-    .TFM_SECURE_STACK (NOLOAD) :
-    {
-        . = ALIGN(128);
-        . += 0x1000;
-    } > RAM_INTERN
-    Image$$TFM_SECURE_STACK$$ZI$$Base = ADDR(.TFM_SECURE_STACK);
-    Image$$TFM_SECURE_STACK$$ZI$$Limit = ADDR(.TFM_SECURE_STACK) + SIZEOF(.TFM_SECURE_STACK);
-
-    .TFM_UNPRIV_SCRATCH (NOLOAD) :
-    {
-        . = ALIGN(32);
-        . += 0x400;
-    } > RAM_INTERN
-    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Base = ADDR(.TFM_UNPRIV_SCRATCH);
-    Image$$TFM_UNPRIV_SCRATCH$$ZI$$Limit = ADDR(.TFM_UNPRIV_SCRATCH) + SIZEOF(.TFM_UNPRIV_SCRATCH);
-
-#elif (TFM_LVL > 1)
-
-    #error("TFM level 2/3 are not supported yet")
-
-#endif
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)
@@ -255,8 +164,6 @@ SECTIONS
         PROVIDE(__end_vector_table__ = .);
     } > RAM_INTERN
 
-#if (TFM_LVL == 0)
-
     .data :
     {
         PROVIDE( __etext = LOADADDR(.data) );
@@ -299,66 +206,6 @@ SECTIONS
         __bss_end__ = .;
     } > RAM_INTERN
 
-#else
-
-    .TFM_DATA :
-    {
-        PROVIDE( __etext = LOADADDR(.TFM_DATA) );
-
-        . = ALIGN(4);
-
-        __data_start__ = .;
-
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-
-        __data_end__ = .;
-
-    } > RAM_INTERN AT>FLASH
-    Image$$ER_TFM_DATA$$RW$$Base = ADDR(.TFM_DATA);
-    Image$$ER_TFM_DATA$$RW$$Limit = ADDR(.TFM_DATA) + SIZEOF(.TFM_DATA);
-
-    .TFM_BSS (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > RAM_INTERN
-    Image$$ER_TFM_DATA$$ZI$$Base = ADDR(.TFM_BSS);
-    Image$$ER_TFM_DATA$$ZI$$Limit = ADDR(.TFM_BSS) + SIZEOF(.TFM_BSS);
-
-#endif
-
-#if (TFM_LVL > 0)
-    /* Application ROM code cannot overlap with TDB internal storage area. */
-    ASSERT((LOADADDR(.TFM_DATA) + SIZEOF(.TFM_DATA)) <= NU_TDB_INTERNAL_STORAGE_START, "Application ROM code cannot overlap with TDB internal storage area.")
-#endif
-
     /* Veneer$$CMSE : */
     .gnu.sgstubs NU_TZ_NSC_START :
     {