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rebase support for MultiTech xDot platform
[XDOT_L151] copy new target CMSIS files from NZ32_SC151 target [XDOT_L151] remove Modtronix code, add HardFault_Handler, update clock configuration to match xDot hardware [XDOT_L151] copy new target HAL files from NZ32_SC151 target [XDOT_L151] update HAL to match xDot hardware [XDOT_L151] add xdot_eeprom.* and xdot_low_power.* files [XDOT_L151] add RTOS support for target Conflicts: rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c [XDOT_L151] match NUCLEO_L152RE startup code for GCC_ARM so RTOS works [XDOT_L151] fix GPIO write failure [XDOT_L151] add XDOT_L151CC target to targets.json [XDOT_L151] change xDot default stack size to 256 bytes and main stack size to 1.5kB [XDOT_L151] update PinNames.h to match rev E hardware - no change to external pinout [XDOT_L151] update style in custom xDot HAL files Conflicts: rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
1 parent 8155513 commit 7836c6e

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‎hal/targets.json

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"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"release_versions": ["2", "5"]
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},
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"XDOT_L151CC": {
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"inherits": ["Target"],
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"core": "Cortex-M3",
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"default_toolchain": "ARM",
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"extra_labels": ["STM", "STM32L1", "STM32L151CC"],
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"supported_toolchains": ["ARM", "GCC_ARM"],
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"progen": {"target": "xdot-l151cc"},
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"device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
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"default_lib": "std"
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},
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"MOTE_L152RC": {
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"inherits": ["Target"],
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"core": "Cortex-M3",

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S

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;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
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;* File Name : startup_stm32l151xc.s
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;* Author : MCD Application Team
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;* Version : V2.2.0
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;* Date : 01-July-2016
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;* Description : STM32L151XC Devices vector for MDK-ARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == Reset_Handler
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* - Configure the system clock
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;* - Branches to __main in the C library (which eventually
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;* calls main()).
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;* After Reset the Cortex-M3 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* COPYRIGHT(c) 2016 STMicroelectronics
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;*
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;* Redistribution and use in source and binary forms, with or without modification,
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;* are permitted provided that the following conditions are met:
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;* 1. Redistributions of source code must retain the above copyright notice,
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;* this list of conditions and the following disclaimer.
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;* 2. Redistributions in binary form must reproduce the above copyright notice,
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;* this list of conditions and the following disclaimer in the documentation
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;* and/or other materials provided with the distribution.
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;* 3. Neither the name of STMicroelectronics nor the names of its contributors
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;* may be used to endorse or promote products derived from this software
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;* without specific prior written permission.
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;*
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;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;
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;*******************************************************************************
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;
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; Amount of memory (in bytes) allocated for Stack
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; Tailor this value to your application needs
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; <h> Stack Configuration
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; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Stack_Size EQU 0x00000400
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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EXPORT __initial_sp
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Stack_Mem SPACE Stack_Size
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__initial_sp EQU 0x20008000 ; Top of RAM (32 KB)
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; <h> Heap Configuration
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; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
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; </h>
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Heap_Size EQU 0x00000200
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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EXPORT __heap_base
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EXPORT __heap_limit
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit EQU (__initial_sp - Stack_Size)
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_IRQHandler ; PVD through EXTI Line detect
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DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line 0
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DCD EXTI1_IRQHandler ; EXTI Line 1
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DCD EXTI2_IRQHandler ; EXTI Line 2
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DCD EXTI3_IRQHandler ; EXTI Line 3
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DCD EXTI4_IRQHandler ; EXTI Line 4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_IRQHandler ; ADC1
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DCD USB_HP_IRQHandler ; USB High Priority
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DCD USB_LP_IRQHandler ; USB Low Priority
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DCD DAC_IRQHandler ; DAC
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DCD COMP_IRQHandler ; COMP through EXTI Line
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DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
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DCD 0 ; Reserved
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DCD TIM9_IRQHandler ; TIM9
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DCD TIM10_IRQHandler ; TIM10
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DCD TIM11_IRQHandler ; TIM11
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
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DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
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DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
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DCD TIM6_IRQHandler ; TIM6
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DCD TIM7_IRQHandler ; TIM7
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DCD 0 ; Reserved
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DCD TIM5_IRQHandler ; TIM5
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DCD SPI3_IRQHandler ; SPI3
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
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DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
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DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
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DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
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DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
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DCD 0 ; Reserved
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DCD COMP_ACQ_IRQHandler ; Comparator Channel Acquisition
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset handler routine
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT __main
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IMPORT SystemInit
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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MemManage_Handler\
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PROC
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EXPORT MemManage_Handler [WEAK]
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B .
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ENDP
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BusFault_Handler\
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PROC
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EXPORT BusFault_Handler [WEAK]
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B .
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ENDP
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UsageFault_Handler\
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PROC
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EXPORT UsageFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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DebugMon_Handler\
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PROC
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EXPORT DebugMon_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT WWDG_IRQHandler [WEAK]
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EXPORT PVD_IRQHandler [WEAK]
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EXPORT TAMPER_STAMP_IRQHandler [WEAK]
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EXPORT RTC_WKUP_IRQHandler [WEAK]
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EXPORT FLASH_IRQHandler [WEAK]
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EXPORT RCC_IRQHandler [WEAK]
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EXPORT EXTI0_IRQHandler [WEAK]
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EXPORT EXTI1_IRQHandler [WEAK]
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EXPORT EXTI2_IRQHandler [WEAK]
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EXPORT EXTI3_IRQHandler [WEAK]
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EXPORT EXTI4_IRQHandler [WEAK]
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EXPORT DMA1_Channel1_IRQHandler [WEAK]
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EXPORT DMA1_Channel2_IRQHandler [WEAK]
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EXPORT DMA1_Channel3_IRQHandler [WEAK]
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EXPORT DMA1_Channel4_IRQHandler [WEAK]
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EXPORT DMA1_Channel5_IRQHandler [WEAK]
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EXPORT DMA1_Channel6_IRQHandler [WEAK]
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EXPORT DMA1_Channel7_IRQHandler [WEAK]
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EXPORT ADC1_IRQHandler [WEAK]
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EXPORT USB_HP_IRQHandler [WEAK]
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EXPORT USB_LP_IRQHandler [WEAK]
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EXPORT DAC_IRQHandler [WEAK]
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EXPORT COMP_IRQHandler [WEAK]
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EXPORT EXTI9_5_IRQHandler [WEAK]
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EXPORT TIM9_IRQHandler [WEAK]
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EXPORT TIM10_IRQHandler [WEAK]
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EXPORT TIM11_IRQHandler [WEAK]
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EXPORT TIM2_IRQHandler [WEAK]
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EXPORT TIM3_IRQHandler [WEAK]
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EXPORT TIM4_IRQHandler [WEAK]
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EXPORT I2C1_EV_IRQHandler [WEAK]
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EXPORT I2C1_ER_IRQHandler [WEAK]
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EXPORT I2C2_EV_IRQHandler [WEAK]
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EXPORT I2C2_ER_IRQHandler [WEAK]
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EXPORT SPI1_IRQHandler [WEAK]
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EXPORT SPI2_IRQHandler [WEAK]
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EXPORT USART1_IRQHandler [WEAK]
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EXPORT USART2_IRQHandler [WEAK]
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EXPORT USART3_IRQHandler [WEAK]
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EXPORT EXTI15_10_IRQHandler [WEAK]
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EXPORT RTC_Alarm_IRQHandler [WEAK]
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EXPORT USB_FS_WKUP_IRQHandler [WEAK]
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EXPORT TIM6_IRQHandler [WEAK]
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EXPORT TIM7_IRQHandler [WEAK]
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EXPORT TIM5_IRQHandler [WEAK]
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EXPORT SPI3_IRQHandler [WEAK]
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EXPORT DMA2_Channel1_IRQHandler [WEAK]
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EXPORT DMA2_Channel2_IRQHandler [WEAK]
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EXPORT DMA2_Channel3_IRQHandler [WEAK]
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EXPORT DMA2_Channel4_IRQHandler [WEAK]
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EXPORT DMA2_Channel5_IRQHandler [WEAK]
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EXPORT COMP_ACQ_IRQHandler [WEAK]
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WWDG_IRQHandler
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PVD_IRQHandler
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TAMPER_STAMP_IRQHandler
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RTC_WKUP_IRQHandler
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FLASH_IRQHandler
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RCC_IRQHandler
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EXTI0_IRQHandler
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EXTI1_IRQHandler
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EXTI2_IRQHandler
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EXTI3_IRQHandler
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EXTI4_IRQHandler
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DMA1_Channel1_IRQHandler
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DMA1_Channel2_IRQHandler
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DMA1_Channel3_IRQHandler
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DMA1_Channel4_IRQHandler
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DMA1_Channel5_IRQHandler
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DMA1_Channel6_IRQHandler
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DMA1_Channel7_IRQHandler
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ADC1_IRQHandler
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USB_HP_IRQHandler
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USB_LP_IRQHandler
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DAC_IRQHandler
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COMP_IRQHandler
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EXTI9_5_IRQHandler
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TIM9_IRQHandler
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TIM10_IRQHandler
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TIM11_IRQHandler
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TIM2_IRQHandler
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TIM3_IRQHandler
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TIM4_IRQHandler
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I2C1_EV_IRQHandler
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I2C1_ER_IRQHandler
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I2C2_EV_IRQHandler
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I2C2_ER_IRQHandler
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SPI1_IRQHandler
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SPI2_IRQHandler
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USART1_IRQHandler
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USART2_IRQHandler
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USART3_IRQHandler
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EXTI15_10_IRQHandler
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RTC_Alarm_IRQHandler
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USB_FS_WKUP_IRQHandler
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TIM6_IRQHandler
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TIM7_IRQHandler
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TIM5_IRQHandler
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SPI3_IRQHandler
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DMA2_Channel1_IRQHandler
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DMA2_Channel2_IRQHandler
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DMA2_Channel3_IRQHandler
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DMA2_Channel4_IRQHandler
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DMA2_Channel5_IRQHandler
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COMP_ACQ_IRQHandler
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B .
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ENDP
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ALIGN
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END

‎hal/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct

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; Scatter-Loading Description File
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; Copyright (c) 2015, STMicroelectronics
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; All rights reserved.
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;
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; Redistribution and use in source and binary forms, with or without
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; modification, are permitted provided that the following conditions are met:
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;
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; 1. Redistributions of source code must retain the above copyright notice,
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; this list of conditions and the following disclaimer.
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; 2. Redistributions in binary form must reproduce the above copyright notice,
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; this list of conditions and the following disclaimer in the documentation
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; and/or other materials provided with the distribution.
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; 3. Neither the name of STMicroelectronics nor the names of its contributors
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; may be used to endorse or promote products derived from this software
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; without specific prior written permission.
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;
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; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; STM32L151RC: 256KB FLASH + 32KB SRAM
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LR_IROM1 0x08000000 0x40000 { ; load region size_region
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ER_IROM1 0x08000000 0x40000 { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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; 73 vectors = 292 bytes (0x124) to be reserved in RAM
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RW_IRAM1 (0x20000000+0x124) (0x8000-0x124) { ; RW data
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.ANY (+RW +ZI)
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}
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}
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