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STM32 TRNG clock configuration
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+32
-8
lines changed

1 file changed

+32
-8
lines changed

targets/TARGET_STM/trng_api.c

Lines changed: 32 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -42,18 +42,17 @@ void trng_init(trng_t *obj)
4242
error("Only 1 RNG instance supported\r\n");
4343
}
4444

45-
#if !defined(TARGET_STM32WB)
46-
/* Because M0 core of WB also needs RG RNG is already clocked by default */
47-
#if defined(RCC_PERIPHCLK_RNG)
45+
#if defined(RCC_PERIPHCLK_RNG) /* STM32L4 / STM32H7 / STM32WB */
46+
47+
#if defined(TARGET_STM32WB)
48+
/* No need to reconfigure RngClockSelection as RNG is already clocked by M0 */
49+
50+
#elif defined(TARGET_STM32H7)
4851
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
4952

5053
/*Select PLLQ output as RNG clock source */
5154
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
52-
#if ((CLOCK_SOURCE) & USE_PLL_MSI)
53-
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_MSI;
54-
#else
5555
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
56-
#endif
5756
#if defined(DUAL_CORE)
5857
uint32_t timeout = HSEM_TIMEOUT;
5958
while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
@@ -65,8 +64,33 @@ void trng_init(trng_t *obj)
6564
#if defined(DUAL_CORE)
6665
LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
6766
#endif /* DUAL_CORE */
67+
68+
#elif defined(TARGET_STM32L4)
69+
/* RNG and USB clocks have the same source, so the common source selection could be already done by USB */
70+
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
71+
72+
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
73+
74+
if (__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY)) {
75+
/* MSI clock is enabled, MSI selected as RNG clock source if not alredy done */
76+
if (__HAL_RCC_GET_RNG_SOURCE() != RCC_RNGCLKSOURCE_MSI) {
77+
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_MSI;
78+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
79+
error("RNG clock configuration error\n");
80+
}
81+
}
82+
} else {
83+
/* MSI clock is not enabled, PLL selected as RNG clock source */
84+
PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_PLL;
85+
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
86+
error("RNG clock configuration error\n");
87+
}
88+
}
89+
90+
#else
91+
#error("RNG clock not configured");
6892
#endif
69-
#endif //!defined(TARGET_STM32WB)
93+
#endif /* defined(RCC_PERIPHCLK_RNG) */
7094

7195
/* RNG Peripheral clock enable */
7296
__HAL_RCC_RNG_CLK_ENABLE();

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