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jeromecoutantABOSTM
jeromecoutant
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DISCO STM32H747I ETHERNET support, but disabled.
Ethernet is disabled by default, because some hardware modifications are required on the board DISCO_H747I. see https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet
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‎features/netsocket/emac-drivers/TARGET_STM/TARGET_STM32H7/TARGET_DISCO_H747I/stm32h7_eth_init.c‎

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/* mbed Microcontroller Library
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* Copyright (c) 2018, STMicroelectronics
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#define ETHERNET 1
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#if (MBED_CONF_TARGET_NETWORK_DEFAULT_INTERFACE_TYPE == ETHERNET)
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#if !defined(DISCO_H747I_ETHERNET_SOLDERBRIGE)
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#error Hardware modifications are required for Ethernet on DISCO_H747I. see https://os.mbed.com/teams/ST/wiki/DISCO_H747I-modifications-for-Ethernet
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#endif
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#endif
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#ifndef USE_USER_DEFINED_HAL_ETH_MSPINIT
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#include "stm32h7xx_hal.h"
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#define ETH_TX_EN_Pin GPIO_PIN_11
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#define ETH_TX_EN_GPIO_Port GPIOG
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#define ETH_TXD1_Pin GPIO_PIN_12
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#define ETH_TXD1_GPIO_Port GPIOG
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#define ETH_TXD0_Pin GPIO_PIN_13
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#define ETH_TXD0_GPIO_Port GPIOG
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#define ETH_MDC_SAI4_D1_Pin GPIO_PIN_1
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#define ETH_MDC_SAI4_D1_GPIO_Port GPIOC
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#define ETH_MDIO_Pin GPIO_PIN_2
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#define ETH_MDIO_GPIO_Port GPIOA
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#define ETH_REF_CLK_Pin GPIO_PIN_1
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#define ETH_REF_CLK_GPIO_Port GPIOA
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#define ETH_CRS_DV_Pin GPIO_PIN_7
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#define ETH_CRS_DV_GPIO_Port GPIOA
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#define ETH_RXD0_Pin GPIO_PIN_4
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#define ETH_RXD0_GPIO_Port GPIOC
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#define ETH_RXD1_Pin GPIO_PIN_5
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#define ETH_RXD1_GPIO_Port GPIOC
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/**
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* Override HAL Eth Init function
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*/
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void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
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{
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GPIO_InitTypeDef GPIO_InitStruct;
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if(heth->Instance == ETH)
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{
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/* Disable DCache for STM32H7 family */
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SCB_DisableDCache();
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/* GPIO Ports Clock Enable */
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__HAL_RCC_GPIOA_CLK_ENABLE();
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// __HAL_RCC_GPIOB_CLK_ENABLE();
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__HAL_RCC_GPIOC_CLK_ENABLE();
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__HAL_RCC_GPIOG_CLK_ENABLE();
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// __HAL_RCC_GPIOH_CLK_ENABLE();
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/* Enable Peripheral clock */
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__HAL_RCC_ETH1MAC_CLK_ENABLE();
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__HAL_RCC_ETH1TX_CLK_ENABLE();
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__HAL_RCC_ETH1RX_CLK_ENABLE();
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/**ETH GPIO Configuration
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PG11 ------> ETH_TX_EN
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PG12 ------> ETH_TXD1
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PG13 ------> ETH_TXD0
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PC1 ------> ETH_MDC
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PA2 ------> ETH_MDIO
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PA1 ------> ETH_REF_CLK
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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*/
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GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
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GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
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GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
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GPIO_InitStruct.Pull = GPIO_NOPULL;
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GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
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GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
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HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
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}
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}
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/**
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* Override HAL Eth DeInit function
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*/
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void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
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{
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if(heth->Instance == ETH)
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{
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/* Peripheral clock disable */
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__HAL_RCC_ETH1MAC_CLK_DISABLE();
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__HAL_RCC_ETH1TX_CLK_DISABLE();
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__HAL_RCC_ETH1RX_CLK_DISABLE();
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/**ETH GPIO Configuration
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PG11 ------> ETH_TX_EN
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PG12 ------> ETH_TXD1
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PG13 ------> ETH_TXD0
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PC1 ------> ETH_MDC
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PA2 ------> ETH_MDIO
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PA1 ------> ETH_REF_CLK
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PA7 ------> ETH_CRS_DV
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PC4 ------> ETH_RXD0
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PC5 ------> ETH_RXD1
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*/
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HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
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HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
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HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
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}
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}
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#endif /* USE_USER_DEFINED_HAL_ETH_MSPINIT */

‎features/netsocket/emac-drivers/TARGET_STM/stm32xx_emac.cpp‎

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@@ -317,9 +317,7 @@ bool STM32_EMAC::low_level_init_successful()
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}
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#else // ETH_IP_VERSION_V2
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{
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uint32_t idx, duplex, speed = 0;
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int32_t PHYLinkState;
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ETH_MACConfigTypeDef MACConf;
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uint32_t idx;
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MPU_Config();
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‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_ARM_STD/stm32h747xI.sct‎

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@@ -41,11 +41,25 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
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}
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RW_DMARxDscrTab 0x30040000 0x60 {
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*(.RxDecripSection)
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}
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RW_DMATxDscrTab 0x30040100 0x140 {
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*(.TxDecripSection)
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}
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RW_Rx_Buffb 0x30040400 0x1800 {
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*(.RxArraySection)
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}
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RW_Eth_Ram 0x30044000 0x4000 {
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*(.ethusbram)
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}
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}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_GCC_ARM/STM32H747xI.ld‎

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/* Check if data + heap + stack exceeds RAM limit */
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ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
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.lwip_sec (NOLOAD) : {
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. = ABSOLUTE(0x30040000);
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*(.RxDecripSection)
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. = ABSOLUTE(0x30040100);
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*(.TxDecripSection)
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. = ABSOLUTE(0x30040400);
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*(.RxArraySection)
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. = ABSOLUTE(0x30044000);
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*(.ethusbram)
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} >RAM_D2 AT> FLASH
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}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM7/TOOLCHAIN_IAR/stm32h747xI.icf‎

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@@ -37,6 +37,10 @@ define memory mem with size = 4G;
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define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
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define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
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// Memory region used for ethernet
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define region eth_mem_region = mem:[from 0x30044000 to 0x30048000 ];
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place in eth_mem_region { section .ethusbram };
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// Stack and Heap
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define symbol __size_cstack__ = MBED_BOOT_STACK_SIZE;
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define symbol __size_heap__ = 0x10000; // 64KB

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