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19 | 19 |
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20 | 20 | #ifndef INITIAL_SP
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21 | 21 |
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22 |
| -#if (defined(TARGET_STM32F051R8) ||\ |
| 22 | +#if (defined(TARGET_STM32L475VG)) |
| 23 | +/* only GCC_ARM and IAR toolchain have the stack on SRAM2 */ |
| 24 | +#if (defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) || defined(__IAR_SYSTEMS_ICC__ )) |
| 25 | +#define INITIAL_SP (0x10008000UL) |
| 26 | +#else |
| 27 | +#define INITIAL_SP (0x20018000UL) |
| 28 | +#endif /* toolchains */ |
| 29 | + |
| 30 | +#elif (defined(TARGET_STM32F051R8) ||\ |
23 | 31 | defined(TARGET_STM32F100RB) ||\
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24 | 32 | defined(TARGET_STM32L031K6) ||\
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25 | 33 | defined(TARGET_STM32L053C8) ||\
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69 | 77 | #define INITIAL_SP (0x20014000UL)
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70 | 78 |
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71 | 79 | #elif (defined(TARGET_STM32F401RE) ||\
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72 |
| - defined(TARGET_STM32L475VG) ||\ |
73 | 80 | defined(TARGET_STM32L476RG) ||\
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74 | 81 | defined(TARGET_STM32L476JG) ||\
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75 | 82 | defined(TARGET_STM32L476VG) ||\
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110 | 117 | #endif
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111 | 118 |
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112 | 119 | #endif // INITIAL_SP
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| 120 | +#if defined(TOOLCHAIN_GCC_ARM) || defined(TOOLCHAIN_GCC_CR) |
| 121 | + extern uint32_t __StackLimit[]; |
| 122 | + extern uint32_t __StackTop[]; |
| 123 | + extern uint32_t __end__[]; |
| 124 | + extern uint32_t __HeapLimit[]; |
| 125 | + #define HEAP_START ((unsigned char*)__end__) |
| 126 | + #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START)) |
| 127 | + #define ISR_STACK_START ((unsigned char*)__StackLimit) |
| 128 | + #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit)) |
| 129 | +#elif defined(__ICCARM__) |
| 130 | + /* No region declarations needed */ |
| 131 | +#endif |
113 | 132 |
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114 | 133 | #endif // MBED_MBED_RTX_H
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