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Fault handler: fix printf format specifiers
1 parent 814d631 commit 82a9072

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1 file changed

+21
-16
lines changed

1 file changed

+21
-16
lines changed

cmsis/TARGET_CORTEX_M/mbed_fault_handler.c

Lines changed: 21 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -14,6 +14,11 @@
1414
* limitations under the License.
1515
*/
1616

17+
#ifndef __STDC_FORMAT_MACROS
18+
#define __STDC_FORMAT_MACROS
19+
#endif
20+
#include <inttypes.h>
21+
1722
#include "device.h"
1823
#include "platform/mbed_error.h"
1924
#include "platform/mbed_interface.h"
@@ -72,37 +77,37 @@ MBED_NOINLINE void print_context_info(void)
7277
{
7378
//Context Regs
7479
for(int i=0;i<13;i++) {
75-
mbed_error_printf("\nR%-4d: %08X", i, ((uint32_t *)&mbed_fault_context)[i]);
80+
mbed_error_printf("\nR%-4d: %08" PRIX32, i, ((uint32_t *)&mbed_fault_context)[i]);
7681
}
7782

78-
mbed_error_printf("\nSP : %08X"
79-
"\nLR : %08X"
80-
"\nPC : %08X"
81-
"\nxPSR : %08X"
82-
"\nPSP : %08X"
83-
"\nMSP : %08X", mbed_fault_context.SP_reg, mbed_fault_context.LR_reg, mbed_fault_context.PC_reg,
83+
mbed_error_printf("\nSP : %08" PRIX32
84+
"\nLR : %08" PRIX32
85+
"\nPC : %08" PRIX32
86+
"\nxPSR : %08" PRIX32
87+
"\nPSP : %08" PRIX32
88+
"\nMSP : %08" PRIX32, mbed_fault_context.SP_reg, mbed_fault_context.LR_reg, mbed_fault_context.PC_reg,
8489
mbed_fault_context.xPSR, mbed_fault_context.PSP, mbed_fault_context.MSP );
8590

8691
//Capture CPUID to get core/cpu info
87-
mbed_error_printf("\nCPUID: %08X", SCB->CPUID);
92+
mbed_error_printf("\nCPUID: %08" PRIX32, SCB->CPUID);
8893

8994
#if !defined(TARGET_M0) && !defined(TARGET_M0P)
9095
//Capture fault information registers to infer the cause of exception
91-
mbed_error_printf("\nHFSR : %08X"
92-
"\nMMFSR: %08X"
93-
"\nBFSR : %08X"
94-
"\nUFSR : %08X"
95-
"\nDFSR : %08X"
96-
"\nAFSR : %08X" ////Split/Capture CFSR into MMFSR, BFSR, UFSR
96+
mbed_error_printf("\nHFSR : %08" PRIX32
97+
"\nMMFSR: %08" PRIX32
98+
"\nBFSR : %08" PRIX32
99+
"\nUFSR : %08" PRIX32
100+
"\nDFSR : %08" PRIX32
101+
"\nAFSR : %08" PRIX32 ////Split/Capture CFSR into MMFSR, BFSR, UFSR
97102
,SCB->HFSR, (0xFF & SCB->CFSR), ((0xFF00 & SCB->CFSR) >> 8), ((0xFFFF0000 & SCB->CFSR) >> 16), SCB->DFSR, SCB->AFSR );
98103

99104
//Print MMFAR only if its valid as indicated by MMFSR
100105
if ((0xFF & SCB->CFSR) & 0x80) {
101-
mbed_error_printf("\nMMFAR: %08X",SCB->MMFAR);
106+
mbed_error_printf("\nMMFAR: %08" PRIX32, SCB->MMFAR);
102107
}
103108
//Print BFAR only if its valid as indicated by BFSR
104109
if (((0xFF00 & SCB->CFSR) >> 8) & 0x80) {
105-
mbed_error_printf("\nBFAR : %08X",SCB->BFAR);
110+
mbed_error_printf("\nBFAR : %08" PRIX32, SCB->BFAR);
106111
}
107112
#endif
108113

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