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14 | 14 | * limitations under the License.
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15 | 15 | */
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16 | 16 |
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| 17 | +#ifndef __STDC_FORMAT_MACROS |
| 18 | +#define __STDC_FORMAT_MACROS |
| 19 | +#endif |
| 20 | +#include <inttypes.h> |
| 21 | + |
17 | 22 | #include "device.h"
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18 | 23 | #include "platform/mbed_error.h"
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19 | 24 | #include "platform/mbed_interface.h"
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@@ -72,37 +77,37 @@ MBED_NOINLINE void print_context_info(void)
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72 | 77 | {
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73 | 78 | //Context Regs
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74 | 79 | for(int i=0;i<13;i++) {
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75 |
| - mbed_error_printf("\nR%-4d: %08X", i, ((uint32_t *)&mbed_fault_context)[i]); |
| 80 | + mbed_error_printf("\nR%-4d: %08" PRIX32, i, ((uint32_t *)&mbed_fault_context)[i]); |
76 | 81 | }
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77 | 82 |
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78 |
| - mbed_error_printf("\nSP : %08X" |
79 |
| - "\nLR : %08X" |
80 |
| - "\nPC : %08X" |
81 |
| - "\nxPSR : %08X" |
82 |
| - "\nPSP : %08X" |
83 |
| - "\nMSP : %08X", mbed_fault_context.SP_reg, mbed_fault_context.LR_reg, mbed_fault_context.PC_reg, |
| 83 | + mbed_error_printf("\nSP : %08" PRIX32 |
| 84 | + "\nLR : %08" PRIX32 |
| 85 | + "\nPC : %08" PRIX32 |
| 86 | + "\nxPSR : %08" PRIX32 |
| 87 | + "\nPSP : %08" PRIX32 |
| 88 | + "\nMSP : %08" PRIX32, mbed_fault_context.SP_reg, mbed_fault_context.LR_reg, mbed_fault_context.PC_reg, |
84 | 89 | mbed_fault_context.xPSR, mbed_fault_context.PSP, mbed_fault_context.MSP );
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85 | 90 |
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86 | 91 | //Capture CPUID to get core/cpu info
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87 |
| - mbed_error_printf("\nCPUID: %08X", SCB->CPUID); |
| 92 | + mbed_error_printf("\nCPUID: %08" PRIX32, SCB->CPUID); |
88 | 93 |
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89 | 94 | #if !defined(TARGET_M0) && !defined(TARGET_M0P)
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90 | 95 | //Capture fault information registers to infer the cause of exception
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91 |
| - mbed_error_printf("\nHFSR : %08X" |
92 |
| - "\nMMFSR: %08X" |
93 |
| - "\nBFSR : %08X" |
94 |
| - "\nUFSR : %08X" |
95 |
| - "\nDFSR : %08X" |
96 |
| - "\nAFSR : %08X" ////Split/Capture CFSR into MMFSR, BFSR, UFSR |
| 96 | + mbed_error_printf("\nHFSR : %08" PRIX32 |
| 97 | + "\nMMFSR: %08" PRIX32 |
| 98 | + "\nBFSR : %08" PRIX32 |
| 99 | + "\nUFSR : %08" PRIX32 |
| 100 | + "\nDFSR : %08" PRIX32 |
| 101 | + "\nAFSR : %08" PRIX32 ////Split/Capture CFSR into MMFSR, BFSR, UFSR |
97 | 102 | ,SCB->HFSR, (0xFF & SCB->CFSR), ((0xFF00 & SCB->CFSR) >> 8), ((0xFFFF0000 & SCB->CFSR) >> 16), SCB->DFSR, SCB->AFSR );
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98 | 103 |
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99 | 104 | //Print MMFAR only if its valid as indicated by MMFSR
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100 | 105 | if ((0xFF & SCB->CFSR) & 0x80) {
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101 |
| - mbed_error_printf("\nMMFAR: %08X",SCB->MMFAR); |
| 106 | + mbed_error_printf("\nMMFAR: %08" PRIX32, SCB->MMFAR); |
102 | 107 | }
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103 | 108 | //Print BFAR only if its valid as indicated by BFSR
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104 | 109 | if (((0xFF00 & SCB->CFSR) >> 8) & 0x80) {
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105 |
| - mbed_error_printf("\nBFAR : %08X",SCB->BFAR); |
| 110 | + mbed_error_printf("\nBFAR : %08" PRIX32, SCB->BFAR); |
106 | 111 | }
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107 | 112 | #endif
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108 | 113 |
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