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jeromecoutantjeromecoutant
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QSPI tests: update STM32 boards configuration
NB: STM directory removed in flash_configs as there is no STM memory
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‎TESTS/mbed_hal/qspi/flash_configs/MX25L51245G_config.h

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/* mbed Microcontroller Library
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* Copyright (c) 2018-2018 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MBED_QSPI_FLASH_MX25L51245G_H
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#define MBED_QSPI_FLASH_MX25L51245G_H
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#define QSPI_FLASH_CHIP_STRING "macronix MX25L51245G"
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// Command for reading status register
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#define QSPI_CMD_RDSR 0x05
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// Command for reading configuration register
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#define QSPI_CMD_RDCR0 0x15
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// Command for writing status/configuration register
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#define QSPI_CMD_WRSR 0x01
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// Command for reading security register
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#define QSPI_CMD_RDSCUR 0x2B
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// Command for setting Reset Enable
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#define QSPI_CMD_RSTEN 0x66
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// Command for setting Reset
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#define QSPI_CMD_RST 0x99
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// Command for setting write enable
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#define QSPI_CMD_WREN 0x06
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// Command for setting write disable
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#define QSPI_CMD_WRDI 0x04
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// WRSR operations max time [us] (datasheet max time + 15%)
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#define QSPI_WRSR_MAX_TIME 34500 // 30ms
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// general wait max time [us]
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#define QSPI_WAIT_MAX_TIME 100000 // 100ms
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// Commands for writing (page programming)
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#define QSPI_CMD_WRITE_1IO 0x02 // 1-1-1 mode
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#define QSPI_CMD_WRITE_4IO 0x38 // 1-4-4 mode
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// write operations max time [us] (datasheet max time + 15%)
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#define QSPI_PAGE_PROG_MAX_TIME 11500 // 10ms
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#define QSPI_PAGE_SIZE 256 // 256B
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#define QSPI_SECTOR_SIZE 4096 // 4kB
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#define QSPI_SECTOR_COUNT 2048 //
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// Commands for reading
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#define QSPI_CMD_READ_1IO_FAST 0x0B // 1-1-1 mode
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#define QSPI_CMD_READ_1IO 0x03 // 1-1-1 mode
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#define QSPI_CMD_READ_2IO 0xBB // 1-2-2 mode
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#define QSPI_CMD_READ_1I2O 0x3B // 1-1-2 mode
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#define QSPI_CMD_READ_4IO 0xEB // 1-4-4 mode
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#define QSPI_CMD_READ_1I4O 0x6B // 1-1-4 mode
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#define QSPI_READ_1IO_DUMMY_CYCLE 0
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#define QSPI_READ_FAST_DUMMY_CYCLE 8
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#define QSPI_READ_2IO_DUMMY_CYCLE 4
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#define QSPI_READ_1I2O_DUMMY_CYCLE 8
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#define QSPI_READ_4IO_DUMMY_CYCLE 6
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#define QSPI_READ_1I4O_DUMMY_CYCLE 8
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// Commands for erasing
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#define QSPI_CMD_ERASE_SECTOR 0x20 // 4kB
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#define QSPI_CMD_ERASE_BLOCK_32 0x52 // 32kB
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#define QSPI_CMD_ERASE_BLOCK_64 0xD8 // 64kB
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#define QSPI_CMD_ERASE_CHIP 0x60 // or 0xC7
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// erase operations max time [us] (datasheet max time + 15%)
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#define QSPI_ERASE_SECTOR_MAX_TIME 480000 // 400 ms
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#define QSPI_ERASE_BLOCK_32_MAX_TIME 1200000 // 1s
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#define QSPI_ERASE_BLOCK_64_MAX_TIME 2400000 // 2s
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// max frequency for basic rw operation (for fast mode)
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#define QSPI_COMMON_MAX_FREQUENCY 32000000
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#define QSPI_STATUS_REG_SIZE 1
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#define QSPI_CONFIG_REG_0_SIZE 2
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#define QSPI_SECURITY_REG_SIZE 1
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#define QSPI_MAX_REG_SIZE 2
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// status register
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#define STATUS_BIT_WIP (1 << 0) // write in progress bit
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#define STATUS_BIT_WEL (1 << 1) // write enable latch
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#define STATUS_BIT_BP0 (1 << 2) //
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#define STATUS_BIT_BP1 (1 << 3) //
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#define STATUS_BIT_BP2 (1 << 4) //
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#define STATUS_BIT_BP3 (1 << 5) //
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#define STATUS_BIT_QE (1 << 6) // Quad Enable
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#define STATUS_BIT_SRWD (1 << 7) // status register write protect
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// configuration register 0
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// bit 0, 1, 2, 4, 5, 7 reserved
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#define CONFIG0_BIT_TB (1 << 3) // Top/Bottom area protect
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#endif // MBED_QSPI_FLASH_MX25L51245G_H

‎TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_F413ZH/flash_config.h

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‎TESTS/mbed_hal/qspi/flash_configs/STM/DISCO_L475VG_IOT01A/flash_config.h

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‎TESTS/mbed_hal/qspi/flash_configs/flash_configs.h

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#define MBED_FLASH_CONFIGS_H
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#if defined(TARGET_DISCO_L475VG_IOT01A)
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#include "STM/DISCO_L475VG_IOT01A/flash_config.h" // MX25R6435F => MX25RXX35F_config.h
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#elif defined(TARGET_NRF52840)
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#include "NORDIC/NRF52840_DK/flash_config.h"
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#include "MX25RXX35F_config.h" // MX25R6435F
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#elif defined(TARGET_DISCO_F413ZH)
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#include "STM/DISCO_F413ZH/flash_config.h" // N25Q128A_config.h
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#include "N25Q128A_config.h" // N25Q128A13EF840F
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#elif defined(TARGET_DISCO_F746NG)
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#include "N25Q128A_config.h"
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#include "N25Q128A_config.h" // N25Q128A13EF840E
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#elif defined(TARGET_DISCO_F469NI)
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#include "N25Q128A_config.h"
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#include "N25Q128A_config.h" // N25Q128A13EF840E
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#elif defined(TARGET_DISCO_F769NI)
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#include "MX25RXX35F_config.h" // MX25L51245G
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#include "MX25L51245G_config.h" // MX25L51245G
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#elif defined(TARGET_DISCO_L476VG)
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#include "N25Q128A_config.h"
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#include "N25Q128A_config.h" // N25Q128A13EF840E
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/* See STM32L476 Errata Sheet, it is not possible to use Dual-/Quad-mode for the command phase */
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#undef QSPI_CMD_READ_DPI
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#undef QSPI_CMD_READ_QPI
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#undef QSPI_CMD_WRITE_DPI
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#undef QSPI_CMD_WRITE_QPI
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#elif defined(TARGET_DISCO_L496AG)
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#include "MX25RXX35F_config.h" // MX25R6435F
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#elif defined(TARGET_NRF52840)
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#include "NORDIC/NRF52840_DK/flash_config.h"
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#elif defined(TARGET_EFM32GG11_STK3701)
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#include "SiliconLabs/EFM32GG11_STK3701/flash_config.h"
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#elif defined(TARGET_K82F)
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#include "NXP/K82F/flash_config.h"
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#elif defined(TARGET_KL82Z)
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#include "NXP/KL82Z/flash_config.h"
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#elif defined(TARGET_LPC546XX)
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#include "NXP/LPC546XX/flash_config.h"
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#endif
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#endif
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#endif // MBED_FLASH_CONFIGS_H

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