Resolved review comments

MubeenHCLite · MubeenHCLite · commit 8622f66b4685 · 2021-07-03T13:22:25.000+05:30
diff --git a/drivers/include/drivers/RawCAN.h b/drivers/include/drivers/RawCAN.h
@@ -31,35 +31,14 @@
 namespace mbed {
 class RawCAN: public CAN {
 public:
-    RawCAN(PinName rd, PinName td);
+    using CAN::CAN;
 
-    /** Initialize CAN interface and set the frequency
-      *
-      * @param rd the read pin
-      * @param td the transmit pin
-      * @param hz the bus frequency in hertz
+    /** Overriding lock apis to create unlocked CAN
       */
-    RawCAN(PinName rd, PinName td, int hz);
 
-    /** Initialize CAN interface
-      *
-      * @param pinmap reference to structure which holds static pinmap
-      * @param td the transmit pin
-      * @param hz the bus frequency in hertz
-      */
-
-    virtual ~RawCAN() {};
+    void lock() override {};
+    void unlock() override {};
 
-    /** Read a CANMessage from the bus.
-     *
-     *  @param msg A CANMessage to read to.
-     *  @param handle message filter handle (0 for any message)
-     *
-     *  @returns
-     *    0 if no message arrived,
-     *    1 if message arrived
-     */
-    int read(CANMessage &msg, int handle = 0);
 };
 }
 
diff --git a/drivers/source/RawCAN.cpp b/drivers/source/RawCAN.cpp
diff --git a/targets/TARGET_STM/TARGET_STM32F0/objects.h b/targets/TARGET_STM/TARGET_STM32F0/objects.h
@@ -155,7 +155,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32F1/objects.h b/targets/TARGET_STM/TARGET_STM32F1/objects.h
@@ -145,7 +145,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32F2/objects.h b/targets/TARGET_STM/TARGET_STM32F2/objects.h
@@ -154,7 +154,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32F3/objects.h b/targets/TARGET_STM/TARGET_STM32F3/objects.h
@@ -142,7 +142,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32F4/objects.h b/targets/TARGET_STM/TARGET_STM32F4/objects.h
@@ -157,7 +157,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32F7/objects.h b/targets/TARGET_STM/TARGET_STM32F7/objects.h
@@ -166,7 +166,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32L4/objects.h b/targets/TARGET_STM/TARGET_STM32L4/objects.h
@@ -156,7 +156,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/TARGET_STM32L5/objects.h b/targets/TARGET_STM/TARGET_STM32L5/objects.h
@@ -156,7 +156,7 @@ struct can_s {
     CAN_HandleTypeDef CanHandle;
     int index;
     int hz;
-    int rxIrqStatus;
+    int rxIrqEnabled;
 };
 #endif
 
diff --git a/targets/TARGET_STM/can_api.c b/targets/TARGET_STM/can_api.c
@@ -778,7 +778,7 @@ void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id)
 {
     irq_handler = handler;
     can_irq_ids[obj->index] = id;
-    obj->rxIrqStatus = false;
+    obj->rxIrqEnabled = false;
 }
 
 void can_irq_free(can_t *obj)
@@ -788,7 +788,7 @@ void can_irq_free(can_t *obj)
     can->IER &= ~(CAN_IT_FMP0 | CAN_IT_FMP1 | CAN_IT_TME | \
                   CAN_IT_ERR | CAN_IT_EPV | CAN_IT_BOF);
     can_irq_ids[obj->index] = 0;
-    obj->rxIrqStatus = DISABLED;
+    obj->rxIrqEnabled = false;
 }
 
 void can_free(can_t *obj)
@@ -1014,7 +1014,7 @@ int can_read(can_t *obj, CAN_Message *msg, int handle)
     /* Release the FIFO */
     can->RF0R |= CAN_RF0R_RFOM0;
 
-    if(obj->rxIrqStatus == ENABLED) {
+    if(obj->rxIrqEnabled == true) {
         __HAL_CAN_ENABLE_IT(&obj->CanHandle, CAN_IT_FMP0);
     }
 
@@ -1031,7 +1031,7 @@ void can_reset(can_t *obj)
 
     /* restore registers state as saved in obj context */
     can_registers_init(obj);
-    obj->rxIrqStatus = DISABLED;
+    obj->rxIrqEnabled = false;
 }
 
 unsigned char can_rderror(can_t *obj)
@@ -1184,7 +1184,7 @@ static void can_irq(CANName name, int id)
     tmp1 = __HAL_CAN_MSG_PENDING(&CanHandle, CAN_FIFO0);
     tmp2 = __HAL_CAN_GET_IT_SOURCE(&CanHandle, CAN_IT_FMP0);
 
-    // In legacy can, reading is the only way to clear rx interrupt. But can_read has mutex locks
+    // In legacy can (bxCAN and earlier), reading is the only way to clear rx interrupt. But can_read has mutex locks
     // since mutexes cannot be used in ISR context, rx interrupt is masked here to temporary disable it
     // rx interrupts will be unamsked in read operation. reads must be deffered to thread context.
     __HAL_CAN_DISABLE_IT(&CanHandle, CAN_IT_FMP0);
@@ -1288,7 +1288,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 ier = CAN_IT_FMP0;
                 irq_n = CAN1_IRQ_RX_IRQN;
                 vector = (uint32_t)&CAN1_IRQ_RX_VECT;
-                obj->rxIrqStatus = ENABLED;
+                obj->rxIrqEnabled = true;
                 break;
             case IRQ_TX:
                 ier = CAN_IT_TME;
@@ -1321,7 +1321,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 ier = CAN_IT_FMP0;
                 irq_n = CAN2_IRQ_RX_IRQN;
                 vector = (uint32_t)&CAN2_IRQ_RX_VECT;
-                obj->rxIrqStatus = ENABLED;
+                obj->rxIrqEnabled = true;
                 break;
             case IRQ_TX:
                 ier = CAN_IT_TME;
@@ -1355,7 +1355,7 @@ void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable)
                 ier = CAN_IT_FMP0;
                 irq_n = CAN3_IRQ_RX_IRQN;
                 vector = (uint32_t)&CAN3_IRQ_RX_VECT;
-                obj->rxIrqStatus = ENABLED;
+                obj->rxIrqEnabled = true;
                 break;
             case IRQ_TX:
                 ier = CAN_IT_TME;
