STM32L4: Add OSPI IP support in fallback QSPI mode

jeromecoutant · LMESTM · commit 8cd00b346879 · 2019-08-23T15:18:48.000+02:00
For STM32 platforms that embed an OSPI IP, we're offering
a QSPI fallback support with this commit.

When OSPI is supported in mbed, we can consider adding full
OSPI support
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/objects.h
@@ -44,16 +44,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F4/common_objects.h b/targets/TARGET_STM/TARGET_STM32F4/common_objects.h
@@ -143,6 +143,23 @@ struct can_s {
 };
 #endif
 
+#if DEVICE_QSPI
+struct qspi_s {
+#if defined(OCTOSPI1)
+    OSPI_HandleTypeDef handle;
+#else
+    QSPI_HandleTypeDef handle;
+#endif
+    QSPIName qspi;
+    PinName io0;
+    PinName io1;
+    PinName io2;
+    PinName io3;
+    PinName sclk;
+    PinName ssel;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32F7/common_objects.h b/targets/TARGET_STM/TARGET_STM32F7/common_objects.h
@@ -142,6 +142,23 @@ struct can_s {
 };
 #endif
 
+#if DEVICE_QSPI
+struct qspi_s {
+#if defined(OCTOSPI1)
+    OSPI_HandleTypeDef handle;
+#else
+    QSPI_HandleTypeDef handle;
+#endif
+    QSPIName qspi;
+    PinName io0;
+    PinName io1;
+    PinName io2;
+    PinName io3;
+    PinName sclk;
+    PinName ssel;
+};
+#endif
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L496xG/objects.h
@@ -58,16 +58,6 @@ struct trng_s {
     RNG_HandleTypeDef handle;
 };
 
-struct qspi_s {
-    QSPI_HandleTypeDef handle;
-    PinName io0;
-    PinName io1;
-    PinName io2;
-    PinName io3;
-    PinName sclk;
-    PinName ssel;
-};
-
 #include "common_objects.h"
 
 #ifdef __cplusplus
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralNames.h
@@ -83,6 +83,11 @@ typedef enum {
     CAN_1 = (int)CAN1_BASE
 } CANName;
 
+typedef enum {
+    QSPI_1 = (int)OCTOSPI1_R_BASE,
+    QSPI_2 = (int)OCTOSPI2_R_BASE
+} QSPIName;
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PeripheralPins.c
@@ -390,3 +390,59 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
     {PH_13,      CAN_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_CAN1)}, // Connected to ARD_D9
     {NC, NC, 0}
 };
+
+//*** QUADSPI ***
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
+    {PB_1,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO0
+    {PE_12,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO0 // Connected to D9
+    {PF_0,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO0 // Connected to PSRAM_A0
+    {PI_11,     QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO0 // Connected to OCTOSPIM_P2_IO0
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
+    {PB_0,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO1 // Connected to ARD_A3
+    {PE_13,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO1 // Connected to D10
+    {PF_1,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO1 // Connected to PSRAM_A1
+    {PI_10,     QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO1 // Connected to OCTOSPIM_P2_IO1
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
+    {PA_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO2 // Connected to ARD_A0
+    {PE_14,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO2 // Connected to D11
+    {PF_2,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO2 // Connected to PSRAM_A2
+    {PI_9,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO2 // Connected to OCTOSPIM_P2_IO2
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
+    {PA_6,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO3 // Connected to SPI2_CS
+    {PE_15,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_IO3 // Connected to D12
+    {PF_3,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO3 // Connected to PSRAM_A3
+    {PH_8,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_IO3 // Connected to OCTOSPI_P2_IO3
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
+//  {PA_3,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_CLK // Connected to STDIO_UART_RX
+    {PB_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_CLK // Connected to USART3_TX
+    {PE_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_CLK // Connected to D7
+    {PF_4,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_CLK // Connected to PSRAM_A4
+    {PF_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)},  // OCTOSPIM_P1_CLK
+    {PI_6,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_CLK // Connected to OCTOSPIM_P2_CLK
+    {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
+//  {PA_2,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_NCS // Connected to STDIO_UART_TX
+    {PA_4,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_OCTOSPIM_P1)},  // OCTOSPIM_P1_NCS // Connected to DCMI_HSYNC
+    {PB_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_NCS // Connected to USART3_RX
+    {PC_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P1)},  // OCTOSPIM_P1_NCS // Connected to uSD_D3
+    {PD_3,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P2)},  // OCTOSPIM_P2_NCS // Connected to PSRAM_CLK
+    {PE_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_OCTOSPIM_P1)},  // OCTOSPIM_P1_NCS // Connected to D8
+    {PG_12,     QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_NCS // Connected to OCTOSPIM_P2_CS
+    {PI_5,      QSPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_OCTOSPIM_P2)},  // OCTOSPIM_P2_NCS // Connected to DCMI_VSYNC
+    {NC, NC, 0}
+};
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/TARGET_DISCO_L4R9I/PinNames.h
@@ -352,6 +352,14 @@ typedef enum {
     SYS_WKUP3 = PE_6,
     SYS_WKUP4 = PA_2,
 
+    /**** QSPI FLASH pins ****/
+    QSPI_FLASH1_IO0 = PI_11,
+    QSPI_FLASH1_IO1 = PI_10,
+    QSPI_FLASH1_IO2 = PI_9,
+    QSPI_FLASH1_IO3 = PH_8,
+    QSPI_FLASH1_SCK = PI_6,
+    QSPI_FLASH1_CSN = PG_12,
+
     /**** STMOD+ pins ****/
     STMOD_1  = PA_6,
     STMOD_2  = PB_15,
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/device/objects.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/objects.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4R9xI/objects.h
diff --git a/targets/TARGET_STM/TARGET_STM32L4/common_objects.h b/targets/TARGET_STM/TARGET_STM32L4/common_objects.h
diff --git a/targets/TARGET_STM/qspi_api.c b/targets/TARGET_STM/qspi_api.c
diff --git a/targets/targets.json b/targets/targets.json
