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[M487] Fix compile warnings with GCC_ARM toolchain
1 parent b31d6f6 commit 99d12b1

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14 files changed

+39
-37
lines changed

14 files changed

+39
-37
lines changed

‎features/FEATURE_LWIP/lwip-interface/lwip-eth/arch/TARGET_NUVOTON/TARGET_M480/m480_netif.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -429,7 +429,9 @@ err_t
429429
/* Packet receive task */
430430

431431
err = sys_sem_new(&RxReadySem, 0);
432-
if(err != ERR_OK) LWIP_ASSERT("RxReadySem creation error", (err == ERR_OK));
432+
if(err != ERR_OK) {
433+
LWIP_ASSERT("RxReadySem creation error", (err == ERR_OK));
434+
}
433435
// In GCC code, DEFAULT_THREAD_STACKSIZE 512 bytes is not enough for rx_task
434436
#if defined (__GNUC__)
435437
// mbed OS 2.0, DEFAULT_THREAD_STACKSIZE*3

‎features/mbedtls/targets/TARGET_NUVOTON/TARGET_M480/sha/sha_alt_hw.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -323,8 +323,8 @@ void crypto_sha_update_nobuf(crypto_sha_context *ctx, const unsigned char *input
323323
int rmn = ilen;
324324
uint32_t sha_ctl_start = (CRPT->HMAC_CTL & ~(CRPT_HMAC_CTL_DMALAST_Msk | CRPT_HMAC_CTL_DMAEN_Msk | CRPT_HMAC_CTL_HMACEN_Msk)) | CRPT_HMAC_CTL_START_Msk;
325325
uint32_t sha_opmode = (CRPT->HMAC_CTL & CRPT_HMAC_CTL_OPMODE_Msk) >> CRPT_HMAC_CTL_OPMODE_Pos;
326-
uint32_t DGST0_old, DGST1_old, DGST2_old, DGST3_old, DGST4_old, DGST5_old, DGST6_old, DGST7_old,
327-
DGST8_old, DGST9_old, DGST10_old, DGST11_old, DGST12_old, DGST13_old, DGST14_old, DGST15_old;
326+
uint32_t DGST0_old = 0, DGST1_old = 0, DGST2_old = 0, DGST3_old = 0, DGST4_old = 0, DGST5_old = 0, DGST6_old = 0, DGST7_old = 0,
327+
DGST8_old = 0, DGST9_old = 0, DGST10_old = 0, DGST11_old = 0, DGST12_old = 0, DGST13_old = 0, DGST14_old = 0, DGST15_old = 0;
328328

329329
while (rmn > 0) {
330330
CRPT->HMAC_CTL = sha_ctl_start;

‎targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/objects.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -128,7 +128,7 @@ struct trng_s {
128128

129129
struct can_s {
130130
CANName can;
131-
char index;
131+
int index;
132132
};
133133
#ifdef __cplusplus
134134
}

‎targets/TARGET_NUVOTON/TARGET_M480/analogin_api.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@ void analogin_init(analogin_t *obj, PinName pin)
5151

5252
const struct nu_modinit_s *modinit = get_modinit(obj->adc, adc_modinit_tab);
5353
MBED_ASSERT(modinit != NULL);
54-
MBED_ASSERT(modinit->modname == obj->adc);
54+
MBED_ASSERT(modinit->modname == (int) obj->adc);
5555

5656
EADC_T *eadc_base = (EADC_T *) NU_MODBASE(obj->adc);
5757

@@ -86,7 +86,7 @@ uint16_t analogin_read_u16(analogin_t *obj)
8686
uint32_t chn = NU_MODSUBINDEX(obj->adc);
8787

8888
EADC_START_CONV(eadc_base, 1 << chn);
89-
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != (1 << chn));
89+
while (EADC_GET_DATA_VALID_FLAG(eadc_base, 1 << chn) != ((uint32_t) (1 << chn)));
9090
uint16_t conv_res_12 = EADC_GET_CONV_DATA(eadc_base, chn);
9191
// Just 12 bits are effective. Convert to 16 bits.
9292
// conv_res_12: 0000 b11b10b9b8 b7b6b5b4 b3b2b1b0

‎targets/TARGET_NUVOTON/TARGET_M480/can_api.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@ void can_init_freq(can_t *obj, PinName rd, PinName td, int hz)
5757

5858
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
5959
MBED_ASSERT(modinit != NULL);
60-
MBED_ASSERT(modinit->modname == obj->can);
60+
MBED_ASSERT(modinit->modname == (int) obj->can);
6161

6262
// Reset this module
6363
SYS_ResetModule(modinit->rsetidx);
@@ -97,7 +97,7 @@ void can_free(can_t *obj)
9797
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
9898

9999
MBED_ASSERT(modinit != NULL);
100-
MBED_ASSERT(modinit->modname == obj->can);
100+
MBED_ASSERT(modinit->modname == (int) obj->can);
101101

102102
// Reset this module
103103
SYS_ResetModule(modinit->rsetidx);
@@ -328,7 +328,7 @@ void can_reset(can_t *obj)
328328
const struct nu_modinit_s *modinit = get_modinit(obj->can, can_modinit_tab);
329329

330330
MBED_ASSERT(modinit != NULL);
331-
MBED_ASSERT(modinit->modname == obj->can);
331+
MBED_ASSERT(modinit->modname == (int) obj->can);
332332

333333
// Reset this module
334334
SYS_ResetModule(modinit->rsetidx);

‎targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_can.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -610,18 +610,18 @@ int32_t CAN_ReadMsgObj(CAN_T *tCAN, uint8_t u8MsgObj, uint8_t u8Release, STR_CAN
610610
static int can_update_spt(int sampl_pt, int tseg, int *tseg1, int *tseg2)
611611
{
612612
*tseg2 = tseg + 1 - (sampl_pt * (tseg + 1)) / 1000;
613-
if (*tseg2 < TSEG2_MIN) {
613+
if (*tseg2 < ((int) TSEG2_MIN)) {
614614
*tseg2 = TSEG2_MIN;
615615
} else {
616616
}
617617

618-
if (*tseg2 > TSEG2_MAX) {
618+
if (*tseg2 > ((int) TSEG2_MAX)) {
619619
*tseg2 = TSEG2_MAX;
620620
} else {
621621
}
622622

623623
*tseg1 = tseg - *tseg2;
624-
if (*tseg1 > TSEG1_MAX) {
624+
if (*tseg1 > ((int) TSEG1_MAX)) {
625625
*tseg1 = TSEG1_MAX;
626626
*tseg2 = tseg - *tseg1;
627627
} else {
@@ -679,14 +679,14 @@ uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
679679
}
680680

681681
/* tseg even = round down, odd = round up */
682-
for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (TSEG1_MIN + TSEG2_MIN) * 2ul; tseg--) {
682+
for (tseg = (TSEG1_MAX + TSEG2_MAX) * 2ul + 1ul; tseg >= (int) ((TSEG1_MIN + TSEG2_MIN) * 2ul); tseg--) {
683683
tsegall = 1ul + tseg / 2ul;
684684
/* Compute all possible tseg choices (tseg=tseg1+tseg2) */
685685
brp = clock_freq / (tsegall * u32BaudRate) + tseg % 2;
686686
/* chose brp step which is possible in system */
687687
brp = (brp / BRP_INC) * BRP_INC;
688688

689-
if ((brp < BRP_MIN) || (brp > BRP_MAX)) {
689+
if ((brp < ((int) BRP_MIN)) || (brp > ((int) BRP_MAX))) {
690690
continue;
691691
}
692692
rate = clock_freq / (brp * tsegall);
@@ -728,7 +728,7 @@ uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate)
728728
sjw = SJW_MAX;
729729
}
730730
/* bt->sjw must not be higher than tseg2 */
731-
if (tseg2 < sjw) {
731+
if (tseg2 < ((int) sjw)) {
732732
sjw = tseg2;
733733
}
734734

‎targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_i2s.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ void I2S_DisableMCLK(I2S_T *i2s)
198198
*/
199199
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
200200
{
201-
i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk) |
201+
i2s->CTL1 = ((i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
202202
(u32TxThreshold << I2S_CTL1_TXTH_Pos) |
203203
(u32RxThreshold << I2S_CTL1_RXTH_Pos));
204204
}
@@ -225,7 +225,7 @@ void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
225225
*/
226226
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
227227
{
228-
i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk) |
228+
i2s->CTL0 = ((i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
229229
(u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
230230
(u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
231231
(u32SyncWidth << I2S_CTL0_PCMSYNC_Pos));

‎targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_sdh.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -360,7 +360,7 @@ uint32_t SDH_Init(SDH_T *sdh)
360360
{
361361
uint32_t volatile i, status;
362362
unsigned int resp;
363-
unsigned int CIDBuffer[4];
363+
uint32_t CIDBuffer[4];
364364
uint32_t volatile u32CmdTimeOut;
365365
SDH_INFO_T *pSD;
366366

@@ -630,7 +630,7 @@ uint32_t SDH_SelectCardType(SDH_T *sdh)
630630
void SDH_Get_SD_info(SDH_T *sdh)
631631
{
632632
unsigned int R_LEN, C_Size, MULT, size;
633-
unsigned int Buffer[4];
633+
uint32_t Buffer[4];
634634
unsigned char *ptr;
635635
SDH_INFO_T *pSD;
636636

@@ -796,7 +796,7 @@ uint32_t SDH_Probe(SDH_T *sdh)
796796
*/
797797
uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount)
798798
{
799-
uint32_t volatile bIsSendCmd = FALSE, buf;
799+
uint32_t volatile bIsSendCmd = FALSE;
800800
uint32_t volatile reg;
801801
uint32_t volatile i, loop, status;
802802
uint32_t blksize = SDH_BLOCK_SIZE;

‎targets/TARGET_NUVOTON/TARGET_M480/device/StdDriver/m480_spim.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -289,7 +289,7 @@ static void SPIM_ReadStatusRegister2(uint8_t dataBuf[], uint32_t u32NRx, uint32_
289289
SwitchNBitOutput(u32NBit);
290290
spim_write(cmdBuf, sizeof (cmdBuf));
291291
SwitchNBitInput(u32NBit);
292-
spim_read(dataBuf, sizeof (dataBuf));
292+
spim_read(dataBuf, u32NRx);
293293
SPIM_SET_SS_EN(0); /* CS deactivated. */
294294
}
295295

@@ -349,7 +349,7 @@ static void SPIM_ReadStatusRegister3(uint8_t dataBuf[], uint32_t u32NRx, uint32_
349349
SwitchNBitOutput(u32NBit);
350350
spim_write(cmdBuf, sizeof (cmdBuf));
351351
SwitchNBitInput(u32NBit);
352-
spim_read(dataBuf, sizeof (dataBuf));
352+
spim_read(dataBuf, u32NRx);
353353
SPIM_SET_SS_EN(0); /* CS deactivated. */
354354
}
355355

@@ -388,7 +388,7 @@ static void SPIM_ReadSecurityRegister(uint8_t dataBuf[], uint32_t u32NRx, uint32
388388
SwitchNBitOutput(u32NBit);
389389
spim_write(cmdBuf, sizeof (cmdBuf));
390390
SwitchNBitInput(u32NBit);
391-
spim_read(dataBuf, sizeof (dataBuf));
391+
spim_read(dataBuf, u32NRx);
392392
SPIM_SET_SS_EN(0); /* CS deactivated. */
393393
}
394394

‎targets/TARGET_NUVOTON/TARGET_M480/i2c_api.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ void i2c_init(i2c_t *obj, PinName sda, PinName scl)
100100

101101
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
102102
MBED_ASSERT(modinit != NULL);
103-
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
103+
MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
104104

105105
// Reset this module
106106
SYS_ResetModule(modinit->rsetidx);
@@ -881,7 +881,7 @@ uint8_t i2c_active(i2c_t *obj)
881881
{
882882
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
883883
MBED_ASSERT(modinit != NULL);
884-
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
884+
MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
885885

886886
// Vector will be changed for async transfer. Use it to judge if async transfer is on-going.
887887
uint32_t vec = NVIC_GetVector(modinit->irq_n);
@@ -909,7 +909,7 @@ static void i2c_enable_vector_interrupt(i2c_t *obj, uint32_t handler, int enable
909909
{
910910
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
911911
MBED_ASSERT(modinit != NULL);
912-
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
912+
MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
913913

914914
if (enable) {
915915
NVIC_SetVector(modinit->irq_n, handler);
@@ -924,7 +924,7 @@ static void i2c_rollback_vector_interrupt(i2c_t *obj)
924924
{
925925
const struct nu_modinit_s *modinit = get_modinit(obj->i2c.i2c, i2c_modinit_tab);
926926
MBED_ASSERT(modinit != NULL);
927-
MBED_ASSERT(modinit->modname == obj->i2c.i2c);
927+
MBED_ASSERT(modinit->modname == (int) obj->i2c.i2c);
928928

929929
struct nu_i2c_var *var = (struct nu_i2c_var *) modinit->var;
930930
i2c_enable_vector_interrupt(obj, (uint32_t) var->vec, 1);

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