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Merge pull request #4511 from c1728p9/fix_m0_devices
Fix Cortex-M0 devices
2 parents 8e76bf6 + 14153e7 commit 9d9ef18

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‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/cmsis_nvic.c

Lines changed: 54 additions & 0 deletions
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/* MPS2 CMSIS Library
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*
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* Copyright (c) 2006-2016 ARM Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. Neither the name of the copyright holder nor the names of its contributors
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* may be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************/
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#include "cmsis_nvic.h"
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#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
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#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
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// int i;
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// Space for dynamic vectors, initialised to allocate in R/W
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static volatile uint32_t* vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Set the vector
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vectors[IRQn + 16] = vector;
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}
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uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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// We can always read vectors at 0x0, as the addresses are remapped
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uint32_t *vectors = (uint32_t*)NVIC_FLASH_VECTOR_ADDRESS;
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// Return the vector
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return vectors[IRQn + 16];
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}

‎targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/cmsis_nvic.h

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,12 +28,27 @@
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*******************************************************************************
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* CMSIS-style functionality to support dynamic vectors
3133
*******************************************************************************/
3234

3335
#ifndef MBED_CMSIS_NVIC_H
3436
#define MBED_CMSIS_NVIC_H
3537

36-
#define NVIC_NUM_VECTORS (16 + 48)
37-
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Location of vectors in RAM
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#include "cmsis.h"
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#define NVIC_NUM_VECTORS (16 + 48)
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#define NVIC_USER_IRQ_OFFSET 16
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
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uint32_t NVIC_GetVector(IRQn_Type IRQn);
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#ifdef __cplusplus
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}
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#endif
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3954
#endif

‎targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.c

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/* mbed Microcontroller Library
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* CMSIS-style functionality to support dynamic vectors
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*******************************************************************************
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* Copyright (c) 2011 ARM Limited. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
8+
* modification, are permitted provided that the following conditions are met:
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*
10+
* 1. Redistributions of source code must retain the above copyright notice,
11+
* this list of conditions and the following disclaimer.
12+
* 2. Redistributions in binary form must reproduce the above copyright notice,
13+
* this list of conditions and the following disclaimer in the documentation
14+
* and/or other materials provided with the distribution.
15+
* 3. Neither the name of ARM Limited nor the names of its contributors
16+
* may be used to endorse or promote products derived from this software
17+
* without specific prior written permission.
18+
*
19+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22+
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
23+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25+
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26+
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27+
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29+
*******************************************************************************
30+
*/
31+
#include "cmsis_nvic.h"
32+
33+
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
34+
* whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
35+
* the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
36+
* to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
37+
*
38+
* If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
39+
* above the vector table before 0x200 will actually go to RAM. So we need to provide
40+
* a solution where the compiler gets the right results based on the memory map
41+
*
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* Option 1 - We allocate and copy 0x200 of RAM rather than just the table
43+
* - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
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* - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
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*
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* Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
47+
* - No flash accesses will go to ram, as there will be nothing there
48+
* - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
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* - RAM overhead: 0, FLASH overhead: 320 bytes
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*
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* Option 2 is the one to go for, as RAM is the most valuable resource
52+
*/
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54+
55+
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM
56+
#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash
57+
/*
58+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
59+
uint32_t *vectors = (uint32_t*)SCB->VTOR;
60+
uint32_t i;
61+
62+
// Copy and switch to dynamic vectors if the first time called
63+
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
64+
uint32_t *old_vectors = vectors;
65+
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
66+
for (i=0; i<NVIC_NUM_VECTORS; i++) {
67+
vectors[i] = old_vectors[i];
68+
}
69+
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
70+
}
71+
vectors[IRQn + 16] = vector;
72+
}
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74+
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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uint32_t *vectors = (uint32_t*)SCB->VTOR;
76+
return vectors[IRQn + 16];
77+
}*/
78+
79+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
80+
// int i;
81+
// Space for dynamic vectors, initialised to allocate in R/W
82+
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
83+
/*
84+
// Copy and switch to dynamic vectors if first time called
85+
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
86+
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
87+
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
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vectors[i] = old_vectors[i];
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}
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LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
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}*/
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93+
// Set the vector
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vectors[IRQn + 16] = vector;
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}
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97+
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
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// We can always read vectors at 0x0, as the addresses are remapped
99+
uint32_t *vectors = (uint32_t*)0;
100+
101+
// Return the vector
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return vectors[IRQn + 16];
103+
}

‎targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.h

Lines changed: 17 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,22 @@
3232
#ifndef MBED_CMSIS_NVIC_H
3333
#define MBED_CMSIS_NVIC_H
3434

35-
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
36-
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)
35+
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
36+
#define NVIC_USER_IRQ_OFFSET 16
37+
38+
#include "nrf51.h"
39+
#include "cmsis.h"
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41+
42+
#ifdef __cplusplus
43+
extern "C" {
44+
#endif
45+
46+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
47+
uint32_t NVIC_GetVector(IRQn_Type IRQn);
48+
49+
#ifdef __cplusplus
50+
}
51+
#endif
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3853
#endif

‎targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.c

Lines changed: 81 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,81 @@
1+
/* mbed Microcontroller Library
2+
* CMSIS-style functionality to support dynamic vectors
3+
*******************************************************************************
4+
* Copyright (c) 2011 ARM Limited. All rights reserved.
5+
* All rights reserved.
6+
*
7+
* Redistribution and use in source and binary forms, with or without
8+
* modification, are permitted provided that the following conditions are met:
9+
*
10+
* 1. Redistributions of source code must retain the above copyright notice,
11+
* this list of conditions and the following disclaimer.
12+
* 2. Redistributions in binary form must reproduce the above copyright notice,
13+
* this list of conditions and the following disclaimer in the documentation
14+
* and/or other materials provided with the distribution.
15+
* 3. Neither the name of ARM Limited nor the names of its contributors
16+
* may be used to endorse or promote products derived from this software
17+
* without specific prior written permission.
18+
*
19+
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20+
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21+
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22+
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
23+
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24+
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25+
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
26+
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27+
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
28+
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29+
*******************************************************************************
30+
*/
31+
#include "cmsis_nvic.h"
32+
33+
/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
34+
* whilst the vector table may only be something like 48 entries (192 bytes, 0xC0),
35+
* the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF
36+
* to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
37+
*
38+
* If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
39+
* above the vector table before 0x200 will actually go to RAM. So we need to provide
40+
* a solution where the compiler gets the right results based on the memory map
41+
*
42+
* Option 1 - We allocate and copy 0x200 of RAM rather than just the table
43+
* - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
44+
* - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
45+
*
46+
* Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there
47+
* - No flash accesses will go to ram, as there will be nothing there
48+
* - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
49+
* - RAM overhead: 0, FLASH overhead: 320 bytes
50+
*
51+
* Option 2 is the one to go for, as RAM is the most valuable resource
52+
*/
53+
54+
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Vectors positioned at start of RAM
55+
56+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
57+
int i;
58+
// Space for dynamic vectors, initialised to allocate in R/W
59+
static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
60+
61+
// Copy and switch to dynamic vectors if first time called
62+
if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {
63+
uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0
64+
for(i = 0; i < NVIC_NUM_VECTORS; i++) {
65+
vectors[i] = old_vectors[i];
66+
}
67+
LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
68+
}
69+
70+
// Set the vector
71+
vectors[IRQn + 16] = vector;
72+
}
73+
74+
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
75+
// We can always read vectors at 0x0, as the addresses are remapped
76+
uint32_t *vectors = (uint32_t*)0;
77+
78+
// Return the vector
79+
return vectors[IRQn + 16];
80+
}
81+

‎targets/TARGET_NXP/TARGET_LPC11UXX/device/cmsis_nvic.h

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -32,7 +32,20 @@
3232
#ifndef MBED_CMSIS_NVIC_H
3333
#define MBED_CMSIS_NVIC_H
3434

35-
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
36-
#define NVIC_RAM_VECTOR_ADDRESS (0x10000000)
35+
#include "cmsis.h"
36+
37+
#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals
38+
#define NVIC_USER_IRQ_OFFSET 16
39+
40+
#ifdef __cplusplus
41+
extern "C" {
42+
#endif
43+
44+
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
45+
uint32_t NVIC_GetVector(IRQn_Type IRQn);
46+
47+
#ifdef __cplusplus
48+
}
49+
#endif
3750

3851
#endif

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