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Cruz Monrreal
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Merge pull request #6666 from bcostm/PULL_REQUEST_CUBE_UPDATE_L0_V1.10.0
STM32L0: Update with CubeL0 V1.10.0
2 parents f7a707a + 893b759 commit a15c2f0

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‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/TOOLCHAIN_ARM_MICRO/startup_stm32l011xx.S

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
22
;* File Name : startup_stm32l011xx.s
33
;* Author : MCD Application Team
4-
;* Version : V1.5.0
5-
;* Date : 8-January-2016
4+
;* Version : V1.7.1
5+
;* Date : 25-November-2016
66
;* Description : STM32l011xx Devices vector table for MDK-ARM toolchain.
77
;* This module performs:
88
;* - Set the initial SP
@@ -12,7 +12,6 @@
1212
;* calls main()).
1313
;* After Reset the Cortex-M0+ processor is in Thread mode,
1414
;* priority is Privileged, and the Stack is set to Main.
15-
;* <<< Use Configuration Wizard in Context Menu >>>
1615
;*******************************************************************************
1716
;*
1817
;* Redistribution and use in source and binary forms, with or without modification,

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l011xx.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l011xx.h
44
* @author MCD Application Team
5-
* @version V1.7.0
6-
* @date 31-May-2016
75
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
86
* This file contains all the peripheral register's definitions, bits
97
* definitions and memory mapping for stm32l011xx devices.
@@ -16,7 +14,7 @@
1614
******************************************************************************
1715
* @attention
1816
*
19-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
17+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2018
*
2119
* Redistribution and use in source and binary forms, with or without modification,
2220
* are permitted provided that the following conditions are met:
@@ -752,7 +750,7 @@ typedef struct
752750

753751
/******************* Bits definition for ADC_CFGR2 register *****************/
754752
#define ADC_CFGR2_TOVS_Pos (9U)
755-
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
753+
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
756754
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
757755
#define ADC_CFGR2_OVSS_Pos (5U)
758756
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@@ -5736,7 +5734,7 @@ typedef struct
57365734
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
57375735
((INSTANCE) == COMP2))
57385736

5739-
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
5737+
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
57405738

57415739
/******************************* CRC Instances ********************************/
57425740
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/stm32l0xx.h

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l0xx.h
44
* @author MCD Application Team
5-
* @version V1.7.0
6-
* @date 31-May-2016
75
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
86
* This file contains all the peripheral register's definitions, bits
97
* definitions and memory mapping for STM32L0xx devices.
@@ -20,7 +18,7 @@
2018
******************************************************************************
2119
* @attention
2220
*
23-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
21+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2422
*
2523
* Redistribution and use in source and binary forms, with or without modification,
2624
* are permitted provided that the following conditions are met:
@@ -114,16 +112,16 @@
114112
#endif /* USE_HAL_DRIVER */
115113

116114
/**
117-
* @brief CMSIS Device version number V1.7.0
115+
* @brief CMSIS Device version number V1.7.1
118116
*/
119117
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
120118
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
121-
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
119+
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
122120
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
123121
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
124-
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
125-
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
126-
|(__STM32L0xx_CMSIS_VERSION_RC))
122+
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
123+
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
124+
|(__STM32L0xx_CMSIS_VERSION_RC))
127125

128126
/**
129127
* @}

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/system_stm32l0xx.h

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,11 @@
22
******************************************************************************
33
* @file system_stm32l0xx.h
44
* @author MCD Application Team
5-
* @version V1.7.0
6-
* @date 31-May-2016
75
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
86
******************************************************************************
97
* @attention
108
*
11-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
9+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
1210
*
1311
* Redistribution and use in source and binary forms, with or without modification,
1412
* are permitted provided that the following conditions are met:

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32l031xx.S

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
22
;* File Name : startup_stm32l053xx.s
33
;* Author : MCD Application Team
4-
;* Version : V1.5.0
5-
;* Date : 8-January-2016
4+
;* Version : V1.7.1
5+
;* Date : 25-November-2016
66
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
77
;* This module performs:
88
;* - Set the initial SP
@@ -12,7 +12,6 @@
1212
;* calls main()).
1313
;* After Reset the Cortex-M0+ processor is in Thread mode,
1414
;* priority is Privileged, and the Stack is set to Main.
15-
;* <<< Use Configuration Wizard in Context Menu >>>
1615
;*******************************************************************************
1716
;*
1817
;* Redistribution and use in source and binary forms, with or without modification,

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_ARM_STD/startup_stm32l031xx.S

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
22
;* File Name : startup_stm32l053xx.s
33
;* Author : MCD Application Team
4-
;* Version : V1.5.0
5-
;* Date : 8-January-2016
4+
;* Version : V1.7.1
5+
;* Date : 25-November-2016
66
;* Description : STM32l053xx Devices vector table for MDK-ARM toolchain.
77
;* This module performs:
88
;* - Set the initial SP
@@ -12,7 +12,6 @@
1212
;* calls main()).
1313
;* After Reset the Cortex-M0+ processor is in Thread mode,
1414
;* priority is Privileged, and the Stack is set to Main.
15-
;* <<< Use Configuration Wizard in Context Menu >>>
1615
;*******************************************************************************
1716
;*
1817
;* Redistribution and use in source and binary forms, with or without modification,

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32l031xx.S

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file startup_stm32l031xx.s
44
* @author MCD Application Team
5-
* @version V1.5.0
6-
* @date 8-January-2016
75
* @brief STM32L031xx Devices vector table for Atollic TrueSTUDIO toolchain.
86
* This module performs:
97
* - Set the initial SP

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/TOOLCHAIN_IAR/startup_stm32l031xx.S

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
22
;* File Name : startup_stm32l031xx.s
33
;* Author : MCD Application Team
4-
;* Version : V1.5.0
5-
;* Date : 8-January-2016
4+
;* Version : V1.7.1
5+
;* Date : 25-November-2016
66
;* Description : STM32L031xx Ultra Low Power Devices vector
77
;* This module performs:
88
;* - Set the initial SP

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l031xx.h

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l031xx.h
44
* @author MCD Application Team
5-
* @version V1.7.0
6-
* @date 31-May-2016
75
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
86
* This file contains all the peripheral register's definitions, bits
97
* definitions and memory mapping for stm32l031xx devices.
@@ -16,7 +14,7 @@
1614
******************************************************************************
1715
* @attention
1816
*
19-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
17+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2018
*
2119
* Redistribution and use in source and binary forms, with or without modification,
2220
* are permitted provided that the following conditions are met:
@@ -761,7 +759,7 @@ typedef struct
761759

762760
/******************* Bits definition for ADC_CFGR2 register *****************/
763761
#define ADC_CFGR2_TOVS_Pos (9U)
764-
#define ADC_CFGR2_TOVS_Msk (0x400001U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
762+
#define ADC_CFGR2_TOVS_Msk (0x1U << ADC_CFGR2_TOVS_Pos) /*!< 0x80000200 */
765763
#define ADC_CFGR2_TOVS ADC_CFGR2_TOVS_Msk /*!< Triggered Oversampling */
766764
#define ADC_CFGR2_OVSS_Pos (5U)
767765
#define ADC_CFGR2_OVSS_Msk (0xFU << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
@@ -5857,7 +5855,7 @@ typedef struct
58575855
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
58585856
((INSTANCE) == COMP2))
58595857

5860-
#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
5858+
#define IS_COMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == COMP12_COMMON)
58615859

58625860
/******************************* CRC Instances ********************************/
58635861
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

‎targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/stm32l0xx.h

Lines changed: 6 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@
22
******************************************************************************
33
* @file stm32l0xx.h
44
* @author MCD Application Team
5-
* @version V1.7.0
6-
* @date 31-May-2016
75
* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
86
* This file contains all the peripheral register's definitions, bits
97
* definitions and memory mapping for STM32L0xx devices.
@@ -20,7 +18,7 @@
2018
******************************************************************************
2119
* @attention
2220
*
23-
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
21+
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
2422
*
2523
* Redistribution and use in source and binary forms, with or without modification,
2624
* are permitted provided that the following conditions are met:
@@ -114,16 +112,16 @@
114112
#endif /* USE_HAL_DRIVER */
115113

116114
/**
117-
* @brief CMSIS Device version number V1.7.0
115+
* @brief CMSIS Device version number V1.7.1
118116
*/
119117
#define __STM32L0xx_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
120118
#define __STM32L0xx_CMSIS_VERSION_SUB1 (0x07) /*!< [23:16] sub1 version */
121-
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
119+
#define __STM32L0xx_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
122120
#define __STM32L0xx_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
123121
#define __STM32L0xx_CMSIS_VERSION ((__STM32L0xx_CMSIS_VERSION_MAIN << 24)\
124-
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
125-
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
126-
|(__STM32L0xx_CMSIS_VERSION_RC))
122+
|(__STM32L0xx_CMSIS_VERSION_SUB1 << 16)\
123+
|(__STM32L0xx_CMSIS_VERSION_SUB2 << 8 )\
124+
|(__STM32L0xx_CMSIS_VERSION_RC))
127125

128126
/**
129127
* @}

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