MCUXpresso: Update the LPC GPIO drivers

Update to the latest SDK GPIO driver

Signed-off-by: Mahesh Mahadevan <[email protected]>

Author: mmahadevan108

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/gpio_api.c

@@ -62,7 +62,7 @@ void gpio_write(gpio_t *obj, int value)
     uint32_t pin_number = obj->pin & 0x1F;
     uint8_t port_number = obj->pin / 32;
 
-    GPIO_WritePinOutput(GPIO, port_number, pin_number, value);
+    GPIO_PinWrite(GPIO, port_number, pin_number, value);
 }
 
 int gpio_read(gpio_t *obj)
@@ -71,5 +71,5 @@ int gpio_read(gpio_t *obj)
     uint32_t pin_number = obj->pin & 0x1F;
     uint8_t port_number = obj->pin / 32;
 
-    return (int)GPIO_ReadPinInput(GPIO, port_number, pin_number);
+    return (int)GPIO_PinRead(GPIO, port_number, pin_number);
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC/port_api.c

@@ -71,12 +71,12 @@ void port_dir(port_t *obj, PinDirection dir)
 
 void port_write(port_t *obj, int value)
 {
-    GPIO_WriteMPort(GPIO, obj->port, value);
+    GPIO_PortMaskedWrite(GPIO, obj->port, value);
 }
 
 int port_read(port_t *obj)
 {
-    return (int)(GPIO_ReadMPort(GPIO, obj->port));
+    return (int)(GPIO_PortMaskedRead(GPIO, obj->port));
 }
 
 #endif

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.c

@@ -1,64 +1,112 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include "fsl_gpio.h"
 
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
 /*******************************************************************************
  * Variables
  ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
 /*******************************************************************************
 * Prototypes
 ************ ******************************************************************/
 
 /*******************************************************************************
  * Code
  ******************************************************************************/
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base   GPIO peripheral base pointer.
+ * param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    assert(port < ARRAY_SIZE(s_gpioClockName));
 
+    /* Upgate the GPIO clock */
+    CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+    /* Reset the GPIO module */
+    RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * // Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * //Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer(Typically GPIO)
+ * param port   GPIO port number
+ * param pin    GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
 void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
 {
     if (config->pinDirection == kGPIO_DigitalInput)
     {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRCLR[port] = 1U << pin;
+#else
         base->DIR[port] &= ~(1U << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
     }
     else
     {
-        base->DIR[port] |= 1U << pin;
         /* Set default output value */
         if (config->outputLogic == 0U)
         {
             base->CLR[port] = (1U << pin);
         }
         else
         {
-            base->PIN[port] = (1U << pin);
+            base->SET[port] = (1U << pin);
         }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRSET[port] = 1U << pin;
+#else
+        base->DIR[port] |= 1U << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
     }
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_gpio.h

@@ -1,31 +1,9 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
  * All rights reserved.
  *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- *   of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- *   list of conditions and the following disclaimer in the documentation and/or
- *   other materials provided with the distribution.
- *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
- *   contributors may be used to endorse or promote products derived from this
- *   software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #ifndef _LPC_GPIO_H_
@@ -46,8 +24,8 @@
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief LPC GPIO driver version 1.0.0. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*! @brief LPC GPIO driver version 2.1.3. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
 /*@}*/
 
 /*! @brief LPC GPIO direction definition */
@@ -80,6 +58,16 @@ extern "C" {
 /*! @name GPIO Configuration */
 /*@{*/
 
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
 /*!
  * @brief Initializes a GPIO pin used by the board.
  *
@@ -124,10 +112,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
  *        - 0: corresponding pin output low-logic level.
  *        - 1: corresponding pin output high-logic level.
  */
-static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
 {
     base->B[port][pin] = output;
 }
+
 /*@}*/
 /*! @name GPIO Input Operations */
 /*@{*/
@@ -142,10 +131,11 @@ static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t
  *        - 0: corresponding pin input low-logic level.
  *        - 1: corresponding pin input high-logic level.
  */
-static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
 {
     return (uint32_t)base->B[port][pin];
 }
+
 /*@}*/
 
 /*!
@@ -155,7 +145,7 @@ static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_
  * @param port GPIO port number
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
 {
     base->SET[port] = mask;
 }
@@ -167,7 +157,7 @@ static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t m
  * @param port GPIO port number
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
 {
     base->CLR[port] = mask;
 }
@@ -179,10 +169,11 @@ static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t
  * @param port GPIO port number
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
 {
     base->NOT[port] = mask;
 }
+
 /*@}*/
 
 /*!
@@ -191,7 +182,7 @@ static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_
  * @param base GPIO peripheral base pointer(Typically GPIO)
  * @param port GPIO port number
  */
-static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
 {
     return (uint32_t)base->PIN[port];
 }
@@ -207,7 +198,7 @@ static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
  * @param port GPIO port number
  * @param mask GPIO pin number macro
  */
-static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
 {
     base->MASK[port] = mask;
 }
@@ -219,7 +210,7 @@ static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mas
  * @param port   GPIO port number
  * @param output  GPIO port output value.
  */
-static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
 {
     base->MPIN[port] = output;
 }
@@ -232,7 +223,7 @@ static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t outp
  * @param port   GPIO port number
  * @retval       masked GPIO port value
  */
-static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
 {
     return (uint32_t)base->MPIN[port];
 }

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/drivers/fsl_reset.h

@@ -46,6 +46,12 @@
  * Definitions
  ******************************************************************************/
 
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.0. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
 /*!
  * @brief Enumeration for peripheral reset control bits
  *
@@ -111,7 +117,7 @@ typedef enum _SYSCON_RSTn
     {                                              \
         kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
     } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
-#define GPIO_RSTS                                    \
+#define GPIO_RSTS_N                                    \
     {                                                \
         kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn \
     } /* Reset bits for GPIO peripheral */