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Reintegration of TARGET_MCU_NRF51822 from master.
It was deleted in the mbed-nordic branch.
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‎hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S

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; mbed Microcontroller Library
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; Copyright (c) 2013 Nordic Semiconductor.
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;Licensed under the Apache License, Version 2.0 (the "License");
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;you may not use this file except in compliance with the License.
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;You may obtain a copy of the License at
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;http://www.apache.org/licenses/LICENSE-2.0
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;Unless required by applicable law or agreed to in writing, software
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;distributed under the License is distributed on an "AS IS" BASIS,
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;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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;See the License for the specific language governing permissions and
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;limitations under the License.
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; Description message
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__initial_sp EQU 0x20004000
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PRESERVE8
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THUMB
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; Vector Table Mapped to Address 0 at Reset
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AREA RESET, DATA, READONLY
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EXPORT __Vectors
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EXPORT __Vectors_End
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EXPORT __Vectors_Size
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__Vectors DCD __initial_sp ; Top of Stack
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK
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DCD RADIO_IRQHandler ;RADIO
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DCD UART0_IRQHandler ;UART0
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DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0
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DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1
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DCD 0 ;Reserved
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DCD GPIOTE_IRQHandler ;GPIOTE
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DCD ADC_IRQHandler ;ADC
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DCD TIMER0_IRQHandler ;TIMER0
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DCD TIMER1_IRQHandler ;TIMER1
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DCD TIMER2_IRQHandler ;TIMER2
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DCD RTC0_IRQHandler ;RTC0
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DCD TEMP_IRQHandler ;TEMP
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DCD RNG_IRQHandler ;RNG
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DCD ECB_IRQHandler ;ECB
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DCD CCM_AAR_IRQHandler ;CCM_AAR
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DCD WDT_IRQHandler ;WDT
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DCD RTC1_IRQHandler ;RTC1
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DCD QDEC_IRQHandler ;QDEC
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DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
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DCD SWI0_IRQHandler ;SWI0
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DCD SWI1_IRQHandler ;SWI1
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DCD SWI2_IRQHandler ;SWI2
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DCD SWI3_IRQHandler ;SWI3
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DCD SWI4_IRQHandler ;SWI4
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DCD SWI5_IRQHandler ;SWI5
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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DCD 0 ;Reserved
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__Vectors_End
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__Vectors_Size EQU __Vectors_End - __Vectors
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AREA |.text|, CODE, READONLY
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; Reset Handler
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NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address
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NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask
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Reset_Handler PROC
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EXPORT Reset_Handler [WEAK]
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IMPORT SystemInit
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IMPORT __main
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LDR R0, =NRF_POWER_RAMON_ADDRESS
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LDR R2, [R0]
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MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
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ORRS R2, R2, R1
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STR R2, [R0]
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__main
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BX R0
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ENDP
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; Dummy Exception Handlers (infinite loops which can be modified)
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NMI_Handler PROC
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EXPORT NMI_Handler [WEAK]
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B .
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ENDP
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HardFault_Handler\
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PROC
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EXPORT HardFault_Handler [WEAK]
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B .
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ENDP
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SVC_Handler PROC
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EXPORT SVC_Handler [WEAK]
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B .
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ENDP
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PendSV_Handler PROC
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EXPORT PendSV_Handler [WEAK]
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B .
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ENDP
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SysTick_Handler PROC
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EXPORT SysTick_Handler [WEAK]
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B .
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ENDP
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Default_Handler PROC
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EXPORT POWER_CLOCK_IRQHandler [WEAK]
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EXPORT RADIO_IRQHandler [WEAK]
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EXPORT UART0_IRQHandler [WEAK]
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EXPORT SPI0_TWI0_IRQHandler [WEAK]
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EXPORT SPI1_TWI1_IRQHandler [WEAK]
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EXPORT GPIOTE_IRQHandler [WEAK]
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EXPORT ADC_IRQHandler [WEAK]
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EXPORT TIMER0_IRQHandler [WEAK]
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EXPORT TIMER1_IRQHandler [WEAK]
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EXPORT TIMER2_IRQHandler [WEAK]
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EXPORT RTC0_IRQHandler [WEAK]
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EXPORT TEMP_IRQHandler [WEAK]
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EXPORT RNG_IRQHandler [WEAK]
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EXPORT ECB_IRQHandler [WEAK]
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EXPORT CCM_AAR_IRQHandler [WEAK]
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EXPORT WDT_IRQHandler [WEAK]
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EXPORT RTC1_IRQHandler [WEAK]
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EXPORT QDEC_IRQHandler [WEAK]
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EXPORT LPCOMP_COMP_IRQHandler [WEAK]
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EXPORT SWI0_IRQHandler [WEAK]
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EXPORT SWI1_IRQHandler [WEAK]
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EXPORT SWI2_IRQHandler [WEAK]
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EXPORT SWI3_IRQHandler [WEAK]
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EXPORT SWI4_IRQHandler [WEAK]
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EXPORT SWI5_IRQHandler [WEAK]
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POWER_CLOCK_IRQHandler
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RADIO_IRQHandler
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UART0_IRQHandler
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SPI0_TWI0_IRQHandler
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SPI1_TWI1_IRQHandler
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GPIOTE_IRQHandler
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ADC_IRQHandler
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TIMER0_IRQHandler
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TIMER1_IRQHandler
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TIMER2_IRQHandler
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RTC0_IRQHandler
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TEMP_IRQHandler
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RNG_IRQHandler
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ECB_IRQHandler
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CCM_AAR_IRQHandler
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WDT_IRQHandler
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RTC1_IRQHandler
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QDEC_IRQHandler
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LPCOMP_COMP_IRQHandler
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SWI0_IRQHandler
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SWI1_IRQHandler
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SWI2_IRQHandler
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SWI3_IRQHandler
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SWI4_IRQHandler
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SWI5_IRQHandler
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B .
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ENDP
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ALIGN
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END
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‎hal/targets/cmsis/TARGET_NORDIC/TARGET_MCU_NRF51822/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct

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;WITHOUT SOFTDEVICE:
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;LR_IROM1 0x00000000 0x00040000 {
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; ER_IROM1 0x00000000 0x00040000 {
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; *.o (RESET, +First)
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; *(InRoot$$Sections)
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; .ANY (+RO)
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; }
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; RW_IRAM1 0x20000000 0x00008000 {
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; .ANY (+RW +ZI)
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; }
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;}
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;
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;WITH SOFTDEVICE:
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LR_IROM1 0x1C000 0x0024000 {
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ER_IROM1 0x1C000 0x0024000 {
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 0x20002800 0x00005800 {
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.ANY (+RW +ZI)
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}
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}

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