Adding QSPI support to SDP-K1 board support package.

Author: malavikasajikumar

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_SDP_K1/PeripheralPins.c

@@ -194,31 +194,31 @@ MBED_WEAK const PinMap PinMap_CAN_TD[] = {
 //*** QUADSPI ***
 
 MBED_WEAK const PinMap PinMap_QSPI_DATA0[] = {
-    {PD_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_DI0
+    {PD_11,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_DI0
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_QSPI_DATA1[] = {
-    {PC_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_DI1
+    {PC_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_DI1
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_QSPI_DATA2[] = {
-    {PF_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // Connected to SDP_QUADSPI_DIO2
+    {PF_7,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_QSPI)},  // Connected to SDP_QUADSPI_DIO2
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_QSPI_DATA3[] = {
-    {PD_13,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // Connected to SDP_QUADSPI_DIO3
+    {PD_13,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_QSPI)},  // Connected to SDP_QUADSPI_DIO3
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_QSPI_SCLK[] = {
-    {PF_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_SCK
+    {PF_10,     QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF9_QSPI)},  // Connected to SDP QUADSPI_SCK
     {NC, NC, 0}
 };
 
 MBED_WEAK const PinMap PinMap_QSPI_SSEL[] = {
-    {PB_6,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF10_QSPI)},  // Connected to QUADSPI_NSS_A
+    {PB_6,      QSPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_QSPI)},  // Connected to QUADSPI_NSS_A
     {NC, NC, 0}
 };

targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_SDP_K1/PinNames.h

@@ -221,6 +221,14 @@ typedef enum {
     SDP_TMR_B    = PE_6,
     SDP_TMR_D    = PC_8,
 
+    /**** QSPI pins ****/
+    SDP_QSPI_NSS = PB_6,
+    SDP_QSPI_D0  = PD_11,
+    SDP_QSPI_D1  = PC_10,
+    SDP_QSPI_D2  = PF_7,
+    SDP_QSPI_D3  = PD_13,
+    SDP_QSPI_SCK = PF_10,
+
     /**** USB pins ****/
     USB_OTG_HS_ULPI_CK = PA_5,
     USB_OTG_HS_ULPI_D0 = PA_3,

targets/targets.json

@@ -4191,6 +4191,7 @@
         },
         "device_has_add": [
             "TRNG",
+            "QSPI",
             "MPU"
         ],
         "device_has_remove": [