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Ganesh Ramachandranadbridge
Ganesh Ramachandran
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adbridge
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Added Support for Toshiba TMPM46B
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‎targets/TARGET_TOSHIBA/TARGET_TMPM46B/Periph_Driver/inc/tmpm46b_adc.h

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/**
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*******************************************************************************
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* @file tmpm46b_adc.h
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* @brief This file provides all the functions prototypes for ADC driver.
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* @version V2.0.2.1
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* @date 2015/02/11
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*
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* DO NOT USE THIS SOFTWARE WITHOUT THE SOFTWARE LISENCE AGREEMENT.
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*
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* (C)Copyright TOSHIBA CORPORATION 2015 All rights reserved
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*******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __TMPM46B_ADC_H
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#define __TMPM46B_ADC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "TMPM46B.h"
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#include "tx04_common.h"
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/** @addtogroup TX04_Periph_Driver
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* @{
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*/
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/** @addtogroup ADC
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* @{
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*/
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/** @defgroup ADC_Exported_Types
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* @{
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*/
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#define IS_ADC_UNIT(param) (((param) == TSB_AD))
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#define ADC_CONVERSION_CLK_10 ((uint32_t)0x00000000)
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#define ADC_CONVERSION_CLK_20 ((uint32_t)0x00000010)
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#define ADC_CONVERSION_CLK_30 ((uint32_t)0x00000020)
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#define ADC_CONVERSION_CLK_40 ((uint32_t)0x00000030)
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#define ADC_CONVERSION_CLK_80 ((uint32_t)0x00000040)
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#define ADC_CONVERSION_CLK_160 ((uint32_t)0x00000050)
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#define ADC_CONVERSION_CLK_320 ((uint32_t)0x00000060)
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#define IS_ADC_HOLD_TIME(param) (((param) == ADC_CONVERSION_CLK_10) || \
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((param) == ADC_CONVERSION_CLK_20) || \
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((param) == ADC_CONVERSION_CLK_30) || \
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((param) == ADC_CONVERSION_CLK_40) || \
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((param) == ADC_CONVERSION_CLK_80) || \
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((param) == ADC_CONVERSION_CLK_160)|| \
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((param) == ADC_CONVERSION_CLK_320))
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#define ADC_FC_DIVIDE_LEVEL_1 ((uint32_t)0x00000000)
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#define ADC_FC_DIVIDE_LEVEL_2 ((uint32_t)0x00000001)
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#define ADC_FC_DIVIDE_LEVEL_4 ((uint32_t)0x00000002)
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#define ADC_FC_DIVIDE_LEVEL_8 ((uint32_t)0x00000003)
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#define ADC_FC_DIVIDE_LEVEL_16 ((uint32_t)0x00000004)
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#define IS_ADC_PRESCALER(param) ((param) <= ADC_FC_DIVIDE_LEVEL_16)
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/* Interrupt generation timing in fixed channel mode */
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#define ADC_INT_SINGLE ((uint32_t)0x00000000)
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#define ADC_INT_CONVERSION_2 ((uint32_t)0x00000010)
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#define ADC_INT_CONVERSION_3 ((uint32_t)0x00000020)
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#define ADC_INT_CONVERSION_4 ((uint32_t)0x00000030)
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#define ADC_INT_CONVERSION_5 ((uint32_t)0x00000040)
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#define ADC_INT_CONVERSION_6 ((uint32_t)0x00000050)
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#define ADC_INT_CONVERSION_7 ((uint32_t)0x00000060)
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#define ADC_INT_CONVERSION_8 ((uint32_t)0x00000070)
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#define IS_ADC_INT_MODE(param) (((param) == ADC_INT_SINGLE) || \
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((param) == ADC_INT_CONVERSION_2) || \
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((param) == ADC_INT_CONVERSION_3) || \
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((param) == ADC_INT_CONVERSION_4) || \
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((param) == ADC_INT_CONVERSION_5) || \
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((param) == ADC_INT_CONVERSION_6) || \
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((param) == ADC_INT_CONVERSION_7) || \
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((param) == ADC_INT_CONVERSION_8))
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typedef enum {
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ADC_AN_00 = 0U, /*!< define for Analog Input channel */
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ADC_AN_01 = 1U,
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ADC_AN_02 = 2U,
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ADC_AN_03 = 3U,
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ADC_AN_04 = 4U,
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ADC_AN_05 = 5U,
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ADC_AN_06 = 6U,
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ADC_AN_07 = 7U,
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} ADC_AINx;
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#define IS_ADC_INPUT_CHANNEL(param) ((param) <= ADC_AN_07)
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#define IS_ADC_SCAN_CHANNEL(start, range) (((start) <= ADC_AN_07) && \
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((range) >= 1U) && \
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(((start) + (range)) <= 8U))
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typedef enum {
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ADC_REG_00 = 0U,
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ADC_REG_01 = 1U,
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ADC_REG_02 = 2U,
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ADC_REG_03 = 3U,
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ADC_REG_04 = 4U,
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ADC_REG_05 = 5U,
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ADC_REG_06 = 6U,
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ADC_REG_07 = 7U,
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ADC_REG_SP = 8U
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} ADC_REGx;
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#define IS_ADC_REG(param) ((param) <= ADC_REG_SP)
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#define ADC_APPLY_VREF_IN_CONVERSION ((uint32_t)0x00000000)
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#define ADC_APPLY_VREF_AT_ANY_TIME ((uint32_t)0x00000001)
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#define IS_ADC_VREF_CTRL(param) (((param) == ADC_APPLY_VREF_IN_CONVERSION) || \
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((param) == ADC_APPLY_VREF_AT_ANY_TIME))
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typedef enum {
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ADC_CMPCR_0 = 0U,
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ADC_CMPCR_1 = 1U
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} ADC_CMPCRx;
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#define IS_ADC_CMPCRx(param) ((param) <= ADC_CMPCR_1)
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#define ADC_EXTERADTRG ((uint32_t)0x00000000)
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#define ADC_INTERTRIGGER ((uint32_t)0x00000001)
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#define IS_ADC_EXTERADTRG(param) (((param) == ADC_EXTERADTRG)|| \
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((param) == ADC_INTERTRIGGER))
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#define IS_ADC_EXTERADTRG_TOP(param) (((param) == ADC_EXTERADTRG)|| \
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((param) == ADC_INTERTRIGGER))
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typedef enum {
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ADC_LARGER_THAN_CMP_REG = 0U,
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ADC_SMALLER_THAN_CMP_REG = 1U
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} ADC_CmpCondition;
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#define IS_ADC_CMPCONDITION(param) ((param) <= ADC_SMALLER_THAN_CMP_REG)
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typedef enum {
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ADC_SEQUENCE_CMP_MODE = 0U,
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ADC_CUMULATION_CMP_MODE = 1U
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} ADC_CmpCntMode;
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#define IS_ADC_CMPMODE(param) ((param) <= ADC_CUMULATION_CMP_MODE)
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typedef enum {
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ADC_TRG_00 = 0U,
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ADC_TRG_01 = 1U,
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ADC_TRG_02 = 2U,
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ADC_TRG_03 = 3U,
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ADC_TRG_04 = 4U,
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ADC_TRG_05 = 5U,
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ADC_TRG_06 = 6U,
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ADC_TRG_07 = 7U,
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ADC_TRG_08 = 8U,
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ADC_TRG_09 = 9U
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} ADC_TRGx;
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#define IS_ADC_TRG(param) ((param) <= ADC_TRG_09)
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/**
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* @brief ADC Monitor Configuration Structure definition
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*/
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typedef struct {
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ADC_AINx CmpChannel; /*!< Select which ADC channel will be used */
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uint32_t CmpCnt; /*!< How many times will valid comparisons be counted, range from 1 to 16 */
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ADC_CmpCondition Condition; /*!< Condition to compare ADC channel with Compare Register */
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ADC_CmpCntMode CntMode; /*!< Mode to compare ADC channel with Compare Register */
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uint32_t CmpValue; /*!< Comparison value to be set in Compare Register, max value is 4095 */
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} ADC_MonitorTypeDef;
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#define IS_ADC_CMPCNT(param) (((param) >= 1U) && ((param) <= 16U))
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#define IS_ADC_CMPVALUE_12BIT(param) ((param) <= 4095U)
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/**
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* @brief Union to store ADC state
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*/
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typedef union {
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uint32_t All;
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struct {
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uint32_t NormalBusy:1; /*!< bit0, Normal A/D conversion busy flag (ADBF) */
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uint32_t NormalComplete:1; /*!< bit1, Normal AD conversion complete flag (EOCF) */
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uint32_t TopBusy:1; /*!< bit2, Top-priority A/D conversion busy flag (HPADBF) */
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uint32_t TopComplete:1; /*!< bit3, Top-priority AD conversion complete flag (HPEOCF) */
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uint32_t Reserved:28; /*!< bit4 to bit 31, reserved */
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} Bit;
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} ADC_State;
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/**
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* @brief Union to store ADC result
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*/
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typedef union {
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uint32_t All;
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struct {
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uint32_t ADResult:12; /*!< bit0 to bit11, store AD result */
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uint32_t Stored:1; /*!< bit12, AD result has been stored */
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uint32_t OverRun:1; /*!< bit13, new AD result is stored before the old one is read */
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uint32_t Reserved:18; /*!< bit14 to bit31, reserved */
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} Bit;
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} ADC_Result;
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/** @} */
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/* End of group ADC_Exported_Types */
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/** @defgroup ADC_Exported_FunctionPrototypes
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* @{
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*/
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void ADC_SWReset(TSB_AD_TypeDef * ADx);
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void ADC_SetClk(TSB_AD_TypeDef * ADx, uint32_t Sample_HoldTime, uint32_t Prescaler_Output);
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void ADC_Start(TSB_AD_TypeDef * ADx);
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void ADC_SetScanMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetRepeatMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetINTMode(TSB_AD_TypeDef * ADx, uint32_t INTMode);
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void ADC_SetInputChannel(TSB_AD_TypeDef * ADx, ADC_AINx InputChannel);
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void ADC_SetScanChannel(TSB_AD_TypeDef * ADx, ADC_AINx StartChannel, uint32_t Range);
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void ADC_SetVrefCut(TSB_AD_TypeDef * ADx, uint32_t VrefCtrl);
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void ADC_SetIdleMode(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetVref(TSB_AD_TypeDef * ADx, FunctionalState NewState);
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void ADC_SetInputChannelTop(TSB_AD_TypeDef * ADx, ADC_AINx TopInputChannel);
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void ADC_StartTopConvert(TSB_AD_TypeDef * ADx);
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void ADC_SetMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, FunctionalState NewState);
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void ADC_ConfigMonitor(TSB_AD_TypeDef * ADx, ADC_CMPCRx ADCMPx, ADC_MonitorTypeDef * Monitor);
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void ADC_SetHWTrg(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
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void ADC_SetHWTrgTop(TSB_AD_TypeDef * ADx, uint32_t HWSrc, FunctionalState NewState);
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ADC_State ADC_GetConvertState(TSB_AD_TypeDef * ADx);
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ADC_Result ADC_GetConvertResult(TSB_AD_TypeDef * ADx, ADC_REGx ADREGx);
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void ADC_EnableTrigger(void);
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void ADC_DisableTrigger(void);
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void ADC_SetTriggerStartup(ADC_TRGx TriggerStartup);
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void ADC_SetTriggerStartupTop(ADC_TRGx TopTriggerStartup);
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/** @} */
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/* End of group ADC_Exported_FunctionPrototypes */
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/** @} */
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/* End of group ADC */
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/** @} */
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/* End of group TX04_Periph_Driver */
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __TMPM46B_ADC_H */

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