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DISCO_H747I Dualcore support
Add 2 targets for DISCO_H747I dualcore: * DISCO_H747I -> for CM7 core * DISCO_H747I_CM4 -> for CM4 core Current restrictions: * TICKLESS deactivated * DeepSleep not supported (DeepSleep wrapped to sleep) Warning: use of the same IP (example I2C1) by both core at the same time is not prevented, but is strongly not recommended. Some Hardware Semaphore are use for common IP, to manage concurrent access by both cores: Flash, GPIO, RCC. Warning: Drag and drop of binary to DISCO_H747I will flash CM7. In order to flash CM4, one can use STM32 CubeProgrammer tool.
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-73
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34 files changed

+3245
-73
lines changed

‎features/mbedtls/targets/TARGET_STM/aes_alt.c

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Original file line numberDiff line numberDiff line change
@@ -103,11 +103,19 @@ void mbedtls_aes_free(mbedtls_aes_context *ctx)
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if (ctx == NULL) {
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return;
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}
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#if defined(DUAL_CORE)
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uint32_t timeout = HSEM_TIMEOUT;
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while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID) && (--timeout != 0)) {
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}
110+
#endif /* DUAL_CORE */
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/* Force the CRYP Periheral Clock Reset */
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__HAL_RCC_CRYP_FORCE_RESET();
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/* Release the CRYP Periheral Clock Reset */
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__HAL_RCC_CRYP_RELEASE_RESET();
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#if defined(DUAL_CORE)
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LL_HSEM_ReleaseLock(HSEM, CFG_HW_RCC_SEMID, HSEM_CR_COREID_CURRENT);
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#endif /* DUAL_CORE */
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mbedtls_zeroize(ctx, sizeof(mbedtls_aes_context));
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}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I/PeripheralPins.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -198,14 +198,14 @@ MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
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// You have to comment all PWM using TIM_MST defined in hal_tick.h file
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// or update python script (check TIM_MST_LIST) and re-run it
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MBED_WEAK const PinMap PinMap_PWM[] = {
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{PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
202-
{PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
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{PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK
204-
{PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK
205-
{PA_1_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK
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{PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO
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{PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO
208-
{PA_2_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO
201+
// {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
202+
// {PA_0_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // Connected to PMOD\#1- USART2_CTS_NSS
203+
// {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2 // Connected to ETH_REF_CLK
204+
// {PA_1_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // Connected to ETH_REF_CLK
205+
{PA_1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 1)}, // TIM15_CH1N // Connected to ETH_REF_CLK
206+
// {PA_2, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3 // Connected to ETH_MDIO
207+
// {PA_2_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // Connected to ETH_MDIO
208+
{PA_2, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 1, 0)}, // TIM15_CH1 // Connected to ETH_MDIO
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{PA_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4 // Connected to ULPI_D0
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{PA_3_ALT0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // Connected to ULPI_D0
211211
{PA_3_ALT1, PWM_15, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM15, 2, 0)}, // TIM15_CH2 // Connected to ULPI_D0

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/startup_stm32h747xx.S

Lines changed: 574 additions & 0 deletions
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‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_ARM_STD/stm32h747xI_CM4.sct

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#! armcc -E
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; Scatter-Loading Description File
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;******************************************************************************
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;* @attention
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;*
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;* Copyright (c) 2019 STMicroelectronics.
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;* All rights reserved.
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;*
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;* This software component is licensed by ST under BSD 3-Clause license,
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;* the "License"; You may not use this file except in compliance with the
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;* License. You may obtain a copy of the License at:
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;* opensource.org/licenses/BSD-3-Clause
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;*
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;******************************************************************************
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#if !defined(MBED_APP_START)
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#define MBED_APP_START 0x08100000
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#endif
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#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 0x100000
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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#define Stack_Size MBED_BOOT_STACK_SIZE
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#define MBED_RAM_START 0x10000000
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#define MBED_RAM_SIZE 0x48000
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#define MBED_VECTTABLE_RAM_START (MBED_RAM_START)
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#define MBED_VECTTABLE_RAM_SIZE 0x298
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#define MBED_RAM0_START (MBED_VECTTABLE_RAM_START + MBED_VECTTABLE_RAM_SIZE)
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#define MBED_RAM0_SIZE (MBED_RAM_SIZE - MBED_VECTTABLE_RAM_SIZE)
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LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
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ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
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*.o (RESET, +First)
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*(InRoot$$Sections)
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.ANY (+RO)
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}
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RW_IRAM1 (MBED_RAM0_START) (MBED_RAM0_SIZE-Stack_Size) { ; RW data
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.ANY (+RW +ZI)
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}
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ARM_LIB_STACK (MBED_RAM0_START+MBED_RAM0_SIZE) EMPTY -Stack_Size { ; stack
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}
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}

‎targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_DISCO_H747I_CM4/TOOLCHAIN_GCC_ARM/STM32H747xI_CM4.ld

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/* Linker script to configure memory regions. */
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/*******************************************************************************
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* @attention
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*
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* Copyright (c) 2019 STMicroelectronics.
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* All rights reserved.
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*
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* This software component is licensed by ST under BSD 3-Clause license,
9+
* the "License"; You may not use this file except in compliance with the
10+
* License. You may obtain a copy of the License at:
11+
* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
14+
*/
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#if !defined(MBED_APP_START)
17+
#define MBED_APP_START 0x08100000
18+
#endif
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20+
#if !defined(MBED_APP_SIZE)
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#define MBED_APP_SIZE 1024K
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#endif
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#if !defined(MBED_BOOT_STACK_SIZE)
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#define MBED_BOOT_STACK_SIZE 0x400
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#endif
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STACK_SIZE = MBED_BOOT_STACK_SIZE;
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MEMORY
31+
{
32+
FLASH (rx) : ORIGIN = MBED_APP_START, LENGTH = MBED_APP_SIZE
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RAM (rwx) : ORIGIN = 0x10000298, LENGTH = 288K - 0x298
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}
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/* Linker script to place sections and symbol values. Should be used together
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* with other linker script that defines memory regions FLASH and RAM.
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* It references following symbols, which must be defined in code:
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* Reset_Handler : Entry of reset handler
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*
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* It defines following symbols, which code can use without definition:
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* __exidx_start
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* __exidx_end
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* __etext
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* __data_start__
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* __preinit_array_start
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* __preinit_array_end
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* __init_array_start
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* __init_array_end
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* __fini_array_start
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* __fini_array_end
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* __data_end__
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* __bss_start__
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* __bss_end__
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* __end__
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* end
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* __HeapLimit
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* __StackLimit
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* __StackTop
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* __stack
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* _estack
62+
*/
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ENTRY(Reset_Handler)
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SECTIONS
66+
{
67+
.text :
68+
{
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KEEP(*(.isr_vector))
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*(.text*)
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KEEP(*(.init))
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KEEP(*(.fini))
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/* .ctors */
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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/* .dtors */
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
87+
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*(.rodata*)
89+
90+
KEEP(*(.eh_frame*))
91+
} > FLASH
92+
93+
.ARM.extab :
94+
{
95+
*(.ARM.extab* .gnu.linkonce.armextab.*)
96+
} > FLASH
97+
98+
__exidx_start = .;
99+
.ARM.exidx :
100+
{
101+
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
102+
} > FLASH
103+
__exidx_end = .;
104+
105+
__etext = .;
106+
_sidata = .;
107+
108+
.data : AT (__etext)
109+
{
110+
__data_start__ = .;
111+
_sdata = .;
112+
*(vtable)
113+
*(.data*)
114+
115+
. = ALIGN(8);
116+
/* preinit data */
117+
PROVIDE_HIDDEN (__preinit_array_start = .);
118+
KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
120+
121+
. = ALIGN(8);
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/* init data */
123+
PROVIDE_HIDDEN (__init_array_start = .);
124+
KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
127+
128+
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. = ALIGN(8);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
135+
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KEEP(*(.jcr*))
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. = ALIGN(8);
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/* All data end */
139+
__data_end__ = .;
140+
_edata = .;
141+
142+
} > RAM
143+
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.bss :
145+
{
146+
. = ALIGN(8);
147+
__bss_start__ = .;
148+
_sbss = .;
149+
*(.bss*)
150+
*(COMMON)
151+
. = ALIGN(8);
152+
__bss_end__ = .;
153+
_ebss = .;
154+
} > RAM
155+
156+
.heap (COPY):
157+
{
158+
__end__ = .;
159+
end = __end__;
160+
*(.heap*)
161+
. = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE;
162+
__HeapLimit = .;
163+
} > RAM
164+
165+
/* .stack_dummy section doesn't contains any symbols. It is only
166+
* used for linker to calculate size of stack sections, and assign
167+
* values to stack symbols later */
168+
.stack_dummy (COPY):
169+
{
170+
*(.stack*)
171+
} > RAM
172+
173+
/* Set stack top to end of RAM, and stack limit move down by
174+
* size of stack_dummy section */
175+
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
176+
_estack = __StackTop;
177+
__StackLimit = __StackTop - STACK_SIZE;
178+
PROVIDE(__stack = __StackTop);
179+
180+
/* Check if data + heap + stack exceeds RAM limit */
181+
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
182+
}

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