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[NUCLEO_L152RE] Change us_ticker timer (32-bit one)
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2 files changed

+15
-95
lines changed

2 files changed

+15
-95
lines changed

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/sleep.c

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -102,17 +102,11 @@ static void SetSysClock_HSI(void)
102102
// MCU SLEEP mode
103103
void sleep(void)
104104
{
105-
// Disable us_ticker update interrupt
106-
TIM_ITConfig(TIM9, TIM_IT_Update, DISABLE);
107-
108105
// Enable PWR clock
109106
RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
110107

111108
// Request to enter SLEEP mode with regulator ON
112109
PWR_EnterSleepMode(PWR_Regulator_ON, PWR_SLEEPEntry_WFI);
113-
114-
// Re-enable us_ticker update interrupt
115-
TIM_ITConfig(TIM9, TIM_IT_Update, ENABLE);
116110
}
117111

118112
// MCU STOP mode (Regulator in LP mode, LSI, HSI and HSE OFF)

libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/us_ticker.c

Lines changed: 15 additions & 89 deletions
Original file line numberDiff line numberDiff line change
@@ -29,127 +29,53 @@
2929
#include "us_ticker_api.h"
3030
#include "PeripheralNames.h"
3131

32-
// Timer selection:
33-
#define TIM_MST TIM9
34-
#define TIM_MST_IRQ TIM9_IRQn
35-
#define TIM_MST_RCC RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM9, ENABLE)
32+
// 32-bit timer selection
33+
#define TIM_MST TIM5
34+
#define TIM_MST_IRQ TIM5_IRQn
35+
#define TIM_MST_RCC RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM5, ENABLE)
3636

37-
static int us_ticker_inited = 0;
38-
static volatile uint32_t SlaveCounter = 0;
39-
static volatile uint32_t oc_int_part = 0;
40-
static volatile uint16_t oc_rem_part = 0;
41-
42-
void set_compare(uint16_t count) {
43-
// Set new output compare value
44-
TIM_SetCompare1(TIM_MST, count);
45-
// Enable IT
46-
TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
47-
}
48-
49-
static void tim_update_oc_irq_handler(void) {
50-
uint16_t cval = TIM_MST->CNT;
51-
52-
// Update interrupt: increment the slave counter
53-
if (TIM_GetITStatus(TIM_MST, TIM_IT_Update) == SET) {
54-
TIM_ClearITPendingBit(TIM_MST, TIM_IT_Update);
55-
SlaveCounter++;
56-
}
57-
58-
// Output compare interrupt: used by interrupt system
59-
if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
60-
TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
61-
if (oc_rem_part > 0) {
62-
set_compare(oc_rem_part); // Finish the remaining time left
63-
oc_rem_part = 0;
64-
}
65-
else {
66-
if (oc_int_part > 0) {
67-
set_compare(0xFFFF);
68-
oc_rem_part = cval; // To finish the counter loop the next time
69-
oc_int_part--;
70-
}
71-
else {
72-
us_ticker_irq_handler();
73-
}
74-
}
75-
}
76-
}
37+
static int us_ticker_inited = 0;
7738

7839
void us_ticker_init(void) {
7940
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
8041

8142
if (us_ticker_inited) return;
8243
us_ticker_inited = 1;
8344

84-
// Enable Timer clock
45+
// Enable timer clock
8546
TIM_MST_RCC;
8647

8748
// Configure time base
8849
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
89-
TIM_TimeBaseStructure.TIM_Period = 0xFFFF;
50+
TIM_TimeBaseStructure.TIM_Period = 0xFFFFFFFF;
9051
TIM_TimeBaseStructure.TIM_Prescaler = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
9152
TIM_TimeBaseStructure.TIM_ClockDivision = 0;
9253
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
9354
TIM_TimeBaseInit(TIM_MST, &TIM_TimeBaseStructure);
94-
95-
// Configure interrupts
96-
TIM_ITConfig(TIM_MST, TIM_IT_Update, ENABLE);
97-
98-
// For 32-bit counter and output compare
99-
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)tim_update_oc_irq_handler);
55+
56+
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)us_ticker_irq_handler);
10057
NVIC_EnableIRQ(TIM_MST_IRQ);
10158

10259
// Enable timer
10360
TIM_Cmd(TIM_MST, ENABLE);
10461
}
10562

10663
uint32_t us_ticker_read() {
107-
uint32_t counter, counter2;
10864
if (!us_ticker_inited) us_ticker_init();
109-
// A situation might appear when Master overflows right after Slave is read and before the
110-
// new (overflowed) value of Master is read. Which would make the code below consider the
111-
// previous (incorrect) value of Slave and the new value of Master, which would return a
112-
// value in the past. Avoid this by computing consecutive values of the timer until they
113-
// are properly ordered.
114-
counter = (uint32_t)(SlaveCounter << 16);
115-
counter += TIM_MST->CNT;
116-
while (1) {
117-
counter2 = (uint32_t)(SlaveCounter << 16);
118-
counter2 += TIM_MST->CNT;
119-
if (counter2 > counter) {
120-
break;
121-
}
122-
counter = counter2;
123-
}
124-
return counter2;
65+
return TIM_MST->CNT;
12566
}
12667

12768
void us_ticker_set_interrupt(unsigned int timestamp) {
128-
int delta = (int)(timestamp - us_ticker_read());
129-
uint16_t cval = TIM_MST->CNT;
130-
131-
if (delta <= 0) { // This event was in the past
132-
us_ticker_irq_handler();
133-
}
134-
else {
135-
oc_int_part = (uint32_t)(delta >> 16);
136-
oc_rem_part = (uint16_t)(delta & 0xFFFF);
137-
if (oc_rem_part <= (0xFFFF - cval)) {
138-
set_compare(cval + oc_rem_part);
139-
oc_rem_part = 0;
140-
} else {
141-
set_compare(0xFFFF);
142-
oc_rem_part = oc_rem_part - (0xFFFF - cval);
143-
}
144-
}
69+
// Set new output compare value
70+
TIM_SetCompare1(TIM_MST, timestamp);
71+
// Enable IT
72+
TIM_ITConfig(TIM_MST, TIM_IT_CC1, ENABLE);
14573
}
14674

14775
void us_ticker_disable_interrupt(void) {
14876
TIM_ITConfig(TIM_MST, TIM_IT_CC1, DISABLE);
14977
}
15078

15179
void us_ticker_clear_interrupt(void) {
152-
if (TIM_GetITStatus(TIM_MST, TIM_IT_CC1) == SET) {
153-
TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
154-
}
80+
TIM_ClearITPendingBit(TIM_MST, TIM_IT_CC1);
15581
}

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