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vmedcyArto Kinnunen
vmedcy
authored and
Arto Kinnunen
committed
PSOC6: update BSP GeneratedSource, add design.modus
1 parent a72472f commit b09e7cd

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68 files changed

+9579
-3212
lines changed

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@
2626

2727
void init_cycfg_all(void)
2828
{
29+
init_cycfg_system();
2930
init_cycfg_clocks();
31+
init_cycfg_routing();
3032
init_cycfg_peripherals();
3133
init_cycfg_pins();
32-
init_cycfg_platform();
33-
init_cycfg_routing();
3434
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -30,11 +30,11 @@ extern "C" {
3030
#endif
3131

3232
#include "cycfg_notices.h"
33+
#include "cycfg_system.h"
3334
#include "cycfg_clocks.h"
35+
#include "cycfg_routing.h"
3436
#include "cycfg_peripherals.h"
3537
#include "cycfg_pins.h"
36-
#include "cycfg_platform.h"
37-
#include "cycfg_routing.h"
3838

3939
void init_cycfg_all(void);
4040

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.c

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -32,14 +32,10 @@ void init_cycfg_clocks(void)
3232
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 0U);
3333

3434
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
35-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 3U);
35+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 1U, 7U);
3636
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 1U);
3737

3838
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
39-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 35U);
39+
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 2U, 108U);
4040
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 2U);
41-
42-
Cy_SysClk_PeriphDisableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
43-
Cy_SysClk_PeriphSetDivider(CY_SYSCLK_DIV_8_BIT, 3U, 0U);
44-
Cy_SysClk_PeriphEnableDivider(CY_SYSCLK_DIV_8_BIT, 3U);
4541
}

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_clocks.h

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -32,14 +32,15 @@
3232
extern "C" {
3333
#endif
3434

35-
#define peri_0_div_8_0_HW CY_SYSCLK_DIV_8_BIT
36-
#define peri_0_div_8_0_NUM 0U
37-
#define peri_0_div_8_1_HW CY_SYSCLK_DIV_8_BIT
38-
#define peri_0_div_8_1_NUM 1U
39-
#define peri_0_div_8_2_HW CY_SYSCLK_DIV_8_BIT
40-
#define peri_0_div_8_2_NUM 2U
41-
#define peri_0_div_8_3_HW CY_SYSCLK_DIV_8_BIT
42-
#define peri_0_div_8_3_NUM 3U
35+
#define CYBSP_CSD_CLK_DIV_ENABLED 1U
36+
#define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
37+
#define CYBSP_CSD_CLK_DIV_NUM 0U
38+
#define CYBSP_CSD_COMM_CLK_DIV_ENABLED 1U
39+
#define CYBSP_CSD_COMM_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
40+
#define CYBSP_CSD_COMM_CLK_DIV_NUM 1U
41+
#define CYBSP_DEBUG_UART_CLK_DIV_ENABLED 1U
42+
#define CYBSP_DEBUG_UART_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
43+
#define CYBSP_DEBUG_UART_CLK_DIV_NUM 2U
4344

4445
void init_cycfg_clocks(void);
4546

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -28,24 +28,24 @@ cy_stc_csd_context_t cy_csd_0_context =
2828
{
2929
.lockKey = CY_CSD_NONE_KEY,
3030
};
31-
const cy_stc_scb_ezi2c_config_t CSD_COMM_config =
31+
const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config =
3232
{
3333
.numberOfAddresses = CY_SCB_EZI2C_ONE_ADDRESS,
3434
.slaveAddress1 = 8U,
3535
.slaveAddress2 = 0U,
3636
.subAddressSize = CY_SCB_EZI2C_SUB_ADDR16_BITS,
3737
.enableWakeFromSleep = false,
3838
};
39-
const cy_stc_scb_uart_config_t KITPROG_UART_config =
39+
const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
4040
{
4141
.uartMode = CY_SCB_UART_STANDARD,
4242
.enableMutliProcessorMode = false,
4343
.smartCardRetryOnNack = false,
4444
.irdaInvertRx = false,
4545
.irdaEnableLowPowerReceiver = false,
46-
.oversample = 12,
46+
.oversample = 8,
4747
.enableMsbFirst = false,
48-
.dataWidth = 9UL,
48+
.dataWidth = 8UL,
4949
.parity = CY_SCB_UART_PARITY_NONE,
5050
.stopBits = CY_SCB_UART_STOP_BITS_1,
5151
.enableInputFilter = false,
@@ -64,14 +64,14 @@ const cy_stc_scb_uart_config_t KITPROG_UART_config =
6464
.txFifoTriggerLevel = 63UL,
6565
.txFifoIntEnableMask = 0UL,
6666
};
67-
const cy_stc_smif_config_t QSPI_config =
67+
const cy_stc_smif_config_t CYBSP_QSPI_config =
6868
{
6969
.mode = (uint32_t)CY_SMIF_NORMAL,
70-
.deselectDelay = QSPI_DESELECT_DELAY,
70+
.deselectDelay = CYBSP_QSPI_DESELECT_DELAY,
7171
.rxClockSel = (uint32_t)CY_SMIF_SEL_INV_INTERNAL_CLK,
7272
.blockEvent = (uint32_t)CY_SMIF_BUS_ERROR,
7373
};
74-
const cy_stc_mcwdt_config_t MCWDT0_config =
74+
const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config =
7575
{
7676
.c0Match = 32768U,
7777
.c1Match = 32768U,
@@ -84,7 +84,7 @@ const cy_stc_mcwdt_config_t MCWDT0_config =
8484
.c0c1Cascade = true,
8585
.c1c2Cascade = false,
8686
};
87-
const cy_stc_rtc_config_t RTC_config =
87+
const cy_stc_rtc_config_t CYBSP_RTC_config =
8888
{
8989
.sec = 0U,
9090
.min = 0U,

‎targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_062_BLE/GeneratedSource/cycfg_peripherals.h

Lines changed: 45 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -38,16 +38,18 @@
3838
extern "C" {
3939
#endif
4040

41+
#define CYBSP_BLE_ENABLED 1U
4142
#define CY_BLE_CORE_CORTEX_M4 4U
4243
#define CY_BLE_CORE_CORTEX_M0P 0U
4344
#define CY_BLE_CORE_DUAL 255U
4445
#ifndef CY_BLE_CORE
4546
#define CY_BLE_CORE 4U
4647
#endif
4748
#define CY_BLE_IRQ bless_interrupt_IRQn
49+
#define CYBSP_CSD_ENABLED 1U
4850
#define CY_CAPSENSE_CORE 4u
4951
#define CY_CAPSENSE_CPU_CLK 100000000u
50-
#define CY_CAPSENSE_PERI_CLK 50000000u
52+
#define CY_CAPSENSE_PERI_CLK 100000000u
5153
#define CY_CAPSENSE_VDDA_MV 3300u
5254
#define CY_CAPSENSE_PERI_DIV_TYPE CY_SYSCLK_DIV_8_BIT
5355
#define CY_CAPSENSE_PERI_DIV_INDEX 0u
@@ -78,45 +80,50 @@ extern "C" {
7880
#define Cmod_PORT_NUM 7u
7981
#define CintA_PORT_NUM 7u
8082
#define CintB_PORT_NUM 7u
81-
#define CapSense_HW CSD0
82-
#define CapSense_IRQ csd_interrupt_IRQn
83-
#define CSD_COMM_HW SCB3
84-
#define CSD_COMM_IRQ scb_3_interrupt_IRQn
85-
#define KITPROG_UART_HW SCB5
86-
#define KITPROG_UART_IRQ scb_5_interrupt_IRQn
87-
#define QSPI_HW SMIF0
88-
#define QSPI_IRQ smif_interrupt_IRQn
89-
#define QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
90-
#define QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
91-
#define QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
92-
#define QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
93-
#define QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
94-
#define QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
95-
#define QSPI_DATALINES0_1 (1UL)
96-
#define QSPI_DATALINES2_3 (1UL)
97-
#define QSPI_DATALINES4_5 (0UL)
98-
#define QSPI_DATALINES6_7 (0UL)
99-
#define QSPI_SS0 (1UL)
100-
#define QSPI_SS1 (0UL)
101-
#define QSPI_SS2 (0UL)
102-
#define QSPI_SS3 (0UL)
103-
#define QSPI_DESELECT_DELAY 7
104-
#define MCWDT0_HW MCWDT_STRUCT0
105-
#define RTC_10_MONTH_OFFSET (28U)
106-
#define RTC_MONTH_OFFSET (24U)
107-
#define RTC_10_DAY_OFFSET (20U)
108-
#define RTC_DAY_OFFSET (16U)
109-
#define RTC_1000_YEAR_OFFSET (12U)
110-
#define RTC_100_YEAR_OFFSET (8U)
111-
#define RTC_10_YEAR_OFFSET (4U)
112-
#define RTC_YEAR_OFFSET (0U)
83+
#define CYBSP_CSD_HW CSD0
84+
#define CYBSP_CSD_IRQ csd_interrupt_IRQn
85+
#define CYBSP_CSD_COMM_ENABLED 1U
86+
#define CYBSP_CSD_COMM_HW SCB3
87+
#define CYBSP_CSD_COMM_IRQ scb_3_interrupt_IRQn
88+
#define CYBSP_DEBUG_UART_ENABLED 1U
89+
#define CYBSP_DEBUG_UART_HW SCB5
90+
#define CYBSP_DEBUG_UART_IRQ scb_5_interrupt_IRQn
91+
#define CYBSP_QSPI_ENABLED 1U
92+
#define CYBSP_QSPI_HW SMIF0
93+
#define CYBSP_QSPI_IRQ smif_interrupt_IRQn
94+
#define CYBSP_QSPI_MEMORY_MODE_ALIGMENT_ERROR (0UL)
95+
#define CYBSP_QSPI_RX_DATA_FIFO_UNDERFLOW (0UL)
96+
#define CYBSP_QSPI_TX_COMMAND_FIFO_OVERFLOW (0UL)
97+
#define CYBSP_QSPI_TX_DATA_FIFO_OVERFLOW (0UL)
98+
#define CYBSP_QSPI_RX_FIFO_TRIGEER_LEVEL (0UL)
99+
#define CYBSP_QSPI_TX_FIFO_TRIGEER_LEVEL (0UL)
100+
#define CYBSP_QSPI_DATALINES0_1 (1UL)
101+
#define CYBSP_QSPI_DATALINES2_3 (1UL)
102+
#define CYBSP_QSPI_DATALINES4_5 (0UL)
103+
#define CYBSP_QSPI_DATALINES6_7 (0UL)
104+
#define CYBSP_QSPI_SS0 (1UL)
105+
#define CYBSP_QSPI_SS1 (0UL)
106+
#define CYBSP_QSPI_SS2 (0UL)
107+
#define CYBSP_QSPI_SS3 (0UL)
108+
#define CYBSP_QSPI_DESELECT_DELAY 7
109+
#define CYBSP_MCWDT0_ENABLED 1U
110+
#define CYBSP_MCWDT0_HW MCWDT_STRUCT0
111+
#define CYBSP_RTC_ENABLED 1U
112+
#define CYBSP_RTC_10_MONTH_OFFSET (28U)
113+
#define CYBSP_RTC_MONTH_OFFSET (24U)
114+
#define CYBSP_RTC_10_DAY_OFFSET (20U)
115+
#define CYBSP_RTC_DAY_OFFSET (16U)
116+
#define CYBSP_RTC_1000_YEAR_OFFSET (12U)
117+
#define CYBSP_RTC_100_YEAR_OFFSET (8U)
118+
#define CYBSP_RTC_10_YEAR_OFFSET (4U)
119+
#define CYBSP_RTC_YEAR_OFFSET (0U)
113120

114121
extern cy_stc_csd_context_t cy_csd_0_context;
115-
extern const cy_stc_scb_ezi2c_config_t CSD_COMM_config;
116-
extern const cy_stc_scb_uart_config_t KITPROG_UART_config;
117-
extern const cy_stc_smif_config_t QSPI_config;
118-
extern const cy_stc_mcwdt_config_t MCWDT0_config;
119-
extern const cy_stc_rtc_config_t RTC_config;
122+
extern const cy_stc_scb_ezi2c_config_t CYBSP_CSD_COMM_config;
123+
extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
124+
extern const cy_stc_smif_config_t CYBSP_QSPI_config;
125+
extern const cy_stc_mcwdt_config_t CYBSP_MCWDT0_config;
126+
extern const cy_stc_rtc_config_t CYBSP_RTC_config;
120127

121128
void init_cycfg_peripherals(void);
122129

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