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RyoheiHagimotoRyoheiHagimoto
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Modified license and code style.
1 parent 0572cf3 commit c34a7b2

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4 files changed

+181
-170
lines changed

4 files changed

+181
-170
lines changed

‎targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_octabus/inc/r_octabus_drv_sc_cfg.h

Lines changed: 43 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,21 @@
1616
*
1717
* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
1818
*********************************************************************************************************************/
19+
/* Copyright (c) 2020 Renesas Electronics Corporation.
20+
* SPDX-License-Identifier: Apache-2.0
21+
*
22+
* Licensed under the Apache License, Version 2.0 (the "License");
23+
* you may not use this file except in compliance with the License.
24+
* You may obtain a copy of the License at
25+
*
26+
* http://www.apache.org/licenses/LICENSE-2.0
27+
*
28+
* Unless required by applicable law or agreed to in writing, software
29+
* distributed under the License is distributed on an "AS IS" BASIS,
30+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31+
* See the License for the specific language governing permissions and
32+
* limitations under the License.
33+
*/
1934
/**********************************************************************************************************************
2035
* File Name : r_octabus_drv_sc_cfg.h
2136
*********************************************************************************************************************/
@@ -40,37 +55,36 @@
4055
External global variables
4156
*********************************************************************************************************************/
4257

43-
static const st_octabus_cfg_t OCTABUS_SC_TABLE[] =
44-
{
58+
static const st_octabus_cfg_t OCTABUS_SC_TABLE[] = {
4559
/* This code is auto-generated. Do not edit manually */
4660
{
47-
OCTABUS_NO_INIT,
48-
OCTABUS_INIT_AT_APP,
49-
0x01000000,
50-
OCTABUS_PRECYCLE_DISABLE,
51-
OCTABUS_TTYPE_DOPI,
52-
5,
53-
5,
54-
0,
55-
OCTABUS_DQSENA_7_CYCLE,
56-
OCTABUS_DVRDLO_DOPI_1P5_CYCLE,
57-
OCTABUS_DVRDHI_DOPI_6P5_CYCLE,
58-
OCTABUS_DVRDCMD_7_CYCLE,
59-
OCTABUS_DVWLO_DOPI_1P5_CYCLE,
60-
OCTABUS_DVWHI_DOPI_1P5_CYCLE,
61-
OCTABUS_DVWCMD_7_CYCLE,
62-
0x00,
63-
0x00,
64-
0x80,
65-
0x00,
66-
OCTABUS_BYTE_ORDER_B1B0B3B2,
67-
0x02,
68-
0x04,
69-
OCTABUS_BYTE_ORDER_B1B0B3B2,
70-
0x02,
71-
0x04,
72-
132000000,
73-
0x00FFFFF0,
61+
OCTABUS_NO_INIT,
62+
OCTABUS_INIT_AT_APP,
63+
0x01000000,
64+
OCTABUS_PRECYCLE_DISABLE,
65+
OCTABUS_TTYPE_DOPI,
66+
5,
67+
5,
68+
0,
69+
OCTABUS_DQSENA_7_CYCLE,
70+
OCTABUS_DVRDLO_DOPI_1P5_CYCLE,
71+
OCTABUS_DVRDHI_DOPI_6P5_CYCLE,
72+
OCTABUS_DVRDCMD_7_CYCLE,
73+
OCTABUS_DVWLO_DOPI_1P5_CYCLE,
74+
OCTABUS_DVWHI_DOPI_1P5_CYCLE,
75+
OCTABUS_DVWCMD_7_CYCLE,
76+
0x00,
77+
0x00,
78+
0x80,
79+
0x00,
80+
OCTABUS_BYTE_ORDER_B1B0B3B2,
81+
0x02,
82+
0x04,
83+
OCTABUS_BYTE_ORDER_B1B0B3B2,
84+
0x02,
85+
0x04,
86+
132000000,
87+
0x00FFFFF0,
7488
},
7589
/* End of modification */
7690
};

‎targets/TARGET_RENESAS/TARGET_RZ_A2XX/common/r_octabus/inc/r_octabus_lld_rza2m_api.h

Lines changed: 29 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,21 @@
1616
*
1717
* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved.
1818
*********************************************************************************************************************/
19+
/* Copyright (c) 2020 Renesas Electronics Corporation.
20+
* SPDX-License-Identifier: Apache-2.0
21+
*
22+
* Licensed under the Apache License, Version 2.0 (the "License");
23+
* you may not use this file except in compliance with the License.
24+
* You may obtain a copy of the License at
25+
*
26+
* http://www.apache.org/licenses/LICENSE-2.0
27+
*
28+
* Unless required by applicable law or agreed to in writing, software
29+
* distributed under the License is distributed on an "AS IS" BASIS,
30+
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
31+
* See the License for the specific language governing permissions and
32+
* limitations under the License.
33+
*/
1934
/**********************************************************************************************************************
2035
* File Name : r_octabus_lld_rza2m_api.h
2136
*********************************************************************************************************************/
@@ -51,8 +66,7 @@
5166
* @enum e_octabus_init_control_t
5267
* emum of Execute initialize function project setting
5368
*/
54-
typedef enum
55-
{
69+
typedef enum {
5670
OCTABUS_NO_INIT = (0), /*!< Not execute initialize function*/
5771
OCTABUS_INIT_AT_LOADER = (1), /*!< Execute initialize function on loader */
5872
OCTABUS_INIT_AT_APP = (2), /*!< Execute initialize function on application */
@@ -62,8 +76,7 @@ typedef enum
6276
* @enum e_octabus_precycle_t
6377
* emum of DVnPC bit of CDSR
6478
*/
65-
typedef enum
66-
{
79+
typedef enum {
6780
OCTABUS_PRECYCLE_DISABLE = (0), /*!< (default value) */
6881
OCTABUS_PRECYCLE_ENABLE = (1), /*!< */
6982
} e_octabus_precycle_t;
@@ -72,8 +85,7 @@ typedef enum
7285
* @enum e_octabus_ttype_t
7386
* emum of DVnTTYP bit of CDSR
7487
*/
75-
typedef enum
76-
{
88+
typedef enum {
7789
OCTABUS_TTYPE_SPI = (0), /*!< */
7890
OCTABUS_TTYPE_SOPI = (1), /*!< */
7991
OCTABUS_TTYPE_DOPI = (2), /*!< (default value) */
@@ -84,8 +96,7 @@ typedef enum
8496
* @enum e_octabus_dqs_ena_cnt_t
8597
* emum of DQSExxx bit of MDTR
8698
*/
87-
typedef enum
88-
{
99+
typedef enum {
89100
OCTABUS_DQSENA_1_CYCLE = (0x0), /*!< */
90101
OCTABUS_DQSENA_2_CYCLE = (0x1), /*!< */
91102
OCTABUS_DQSENA_3_CYCLE = (0x2), /*!< */
@@ -108,8 +119,7 @@ typedef enum
108119
* @enum e_octabus_dvrdlo_t
109120
* emum of DVRDLOn field of DRCSTR
110121
*/
111-
typedef enum
112-
{
122+
typedef enum {
113123
OCTABUS_DVRDLO_DOPI_1P5_CYCLE = (0), /*!< 1.5 clock cycle */
114124
OCTABUS_DVRDLO_DOPI_2P5_CYCLE = (1), /*!< 2.5 clock cycle */
115125
OCTABUS_DVRDLO_DOPI_3P5_CYCLE = (2), /*!< 3.5 clock cycle */
@@ -124,8 +134,7 @@ typedef enum
124134
* @enum e_octabus_dvrdhi_t
125135
* emum of DVRDHIn field of DRCSTR
126136
*/
127-
typedef enum
128-
{
137+
typedef enum {
129138
OCTABUS_DVRDHI_DOPI_6P5_CYCLE = (5), /*!< 6.5 clock cycle */
130139
OCTABUS_DVRDHI_DOPI_7P5_CYCLE = (6), /*!< 7.5 clock cycle */
131140
OCTABUS_DVRDHI_DOPI_8P5_CYCLE = (7), /*!< 8.5 clock cycle */
@@ -143,8 +152,7 @@ typedef enum
143152
* @enum e_octabus_dvrcmd_t
144153
* emum of DVRDCMDn field of DRCSTR
145154
*/
146-
typedef enum
147-
{
155+
typedef enum {
148156
OCTABUS_DVRDCMD_2_CYCLE = (0), /*!< 2 clock cycle */
149157
OCTABUS_DVRDCMD_5_CYCLE = (1), /*!< 5 clock cycle */
150158
OCTABUS_DVRDCMD_7_CYCLE = (2), /*!< 7 clock cycle */
@@ -159,8 +167,7 @@ typedef enum
159167
* @enum e_octabus_dvwlo_t
160168
* emum of DVWLOn field of DWCSTR
161169
*/
162-
typedef enum
163-
{
170+
typedef enum {
164171
OCTABUS_DVWLO_DOPI_1P5_CYCLE = (0), /*!< 1.5 clock cycle */
165172
OCTABUS_DVWLO_DOPI_2P5_CYCLE = (1), /*!< 2.5 clock cycle */
166173
OCTABUS_DVWLO_DOPI_3P5_CYCLE = (2), /*!< 3.5 clock cycle */
@@ -175,8 +182,7 @@ typedef enum
175182
* @enum e_octabus_dvwhi_t
176183
* emum of DVWHIn field of DWCSTR
177184
*/
178-
typedef enum
179-
{
185+
typedef enum {
180186
OCTABUS_DVWHI_DOPI_1P5_CYCLE = (0), /*!< 1.5 clock cycle */
181187
OCTABUS_DVWHI_DOPI_2P5_CYCLE = (1), /*!< 2.5 clock cycle */
182188
OCTABUS_DVWHI_DOPI_3P5_CYCLE = (2), /*!< 3.5 clock cycle */
@@ -199,8 +205,7 @@ typedef enum
199205
* @enum e_octabus_dvwcmd_t
200206
* emum of DVWCMDn field of DWCSTR
201207
*/
202-
typedef enum
203-
{
208+
typedef enum {
204209
OCTABUS_DVWCMD_2_CYCLE = (0), /*!< 2 clock cycle */
205210
OCTABUS_DVWCMD_5_CYCLE = (1), /*!< 5 clock cycle */
206211
OCTABUS_DVWCMD_7_CYCLE = (2), /*!< 7 clock cycle */
@@ -215,16 +220,14 @@ typedef enum
215220
* @enum e_octabus_byte_order_t
216221
* emum of MxOn field of MRWCSR
217222
*/
218-
typedef enum
219-
{
223+
typedef enum {
220224
OCTABUS_BYTE_ORDER_B0B1B2B3 = (0), /*!< Byte order is byte0, byte1, byte2, byte3 */
221225
OCTABUS_BYTE_ORDER_B1B0B3B2 = (1), /*!< Byte order is byte1, byte0, byte3, byte2 */
222226
} e_octabus_byte_order_t;
223227

224228

225229

226-
typedef struct
227-
{
230+
typedef struct {
228231
e_octabus_init_control_t init_flag0; /*!< Initialize procedure excute project */
229232
e_octabus_init_control_t init_flag1; /*!< Initialize procedure excute project */
230233
uint32_t devsize1; /*!< Size of RAM(Byte) */
@@ -254,8 +257,7 @@ typedef struct
254257
uint32_t acar1; /*!< Auto-Calibration Address value of RAM */
255258
} st_octabus_cfg_t;
256259

257-
typedef struct
258-
{
260+
typedef struct {
259261
uint32_t dcr_value;
260262
uint32_t dar_value;
261263
uint32_t dcsr_value;
@@ -325,7 +327,7 @@ int_t R_OCTABUS_AutoCalib(const st_octabus_cfg_t *p_cfg);
325327
* @fn R_OCTABUS_WriteConfigMode
326328
*
327329
* @brief Write data in configuration mode
328-
330+
329331
* @param[in] p_config : register setting data for configuration mode
330332
* @param[in] write_value : write data
331333
* @retval none

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