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targets/TARGET_NUVOTON/TARGET_M2351/TARGET_NUMAKER_PFM_M2351 Expand file tree Collapse file tree 1 file changed +6
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lines changed Original file line number Diff line number Diff line change @@ -55,15 +55,11 @@ void mbed_sdk_init(void)
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/* Wait for HIRC48 clock ready */
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CLK_WaitClockReady (CLK_STATUS_HIRC48STB_Msk );
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+
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+ #if defined(NU_CHIP_MAJOR ) && (NU_CHIP_MAJOR == 1UL )
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/* NOTE: There is a reset halt issue with PLL in A version. Work around it
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* by using HIRC48 instead of PLL as HCLK clock source. */
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- #if 0
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- /* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
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- CLK_SetHCLK (CLK_CLKSEL0_HCLKSEL_HIRC , CLK_CLKDIV0_HCLK (1 ));
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-
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- /* Set core clock as 48M from PLL */
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- CLK_SetCoreClock (FREQ_48MHZ );
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- #else
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+
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/* Trim HIRC48 to 48M against LXT */
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/* Reset TISTS48M status flags */
@@ -90,6 +86,9 @@ void mbed_sdk_init(void)
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}
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CLK_SetHCLK (CLK_CLKSEL0_HCLKSEL_HIRC48 , CLK_CLKDIV0_HCLK (1UL ));
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+ #else
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+ /* Set core clock as 64M from PLL */
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+ CLK_SetCoreClock (FREQ_64MHZ );
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#endif
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/* Update System Core Clock */
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