Merge pull request #7237 from li-ho/ev-cog-cache

Cruz Monrreal · web-flow · commit c3bdfad392d7 · 2018-06-18T17:18:51.000-05:00
Enable COG boards instruction cache
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TARGET_EV_COG_AD3029LZ/device/system_ADuCM3029.c
@@ -157,8 +157,8 @@ void SramInit(void)
     adi_system_EnableRetention(ADI_SRAM_BANK_2, true);
     /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */
     adi_system_EnableISRAM(false);
-    /* To disable the instruction cache  */
-    adi_system_EnableCache(false);
+    /* To enable the 4K instruction cache out of DSRAM */
+    adi_system_EnableCache(true);
 }
 
 
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_ARM_STD/ADuCM3029.sct
@@ -74,7 +74,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
         .ANY (+RW +ZI)
     }
 
-    ADUCM_IRAM3 0x20040000 0x8000 { ; non-retainable memory region
+    ADUCM_IRAM3 0x20040000 0x7000 { ; non-retainable memory region
          .ANY (+RW +ZI)
     }
 }
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_GCC_ARM/ADuCM3029.ld
@@ -27,7 +27,7 @@ MEMORY
   DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 16k - 0x200
   DSRAM_C (rwx) : ORIGIN = 0x20004000, LENGTH = 16k
   /* SRAM bank 3 */
-  DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 32k
+  DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 28k
 }
 
 /* Library configurations */
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM302X/TARGET_ADUCM3029/TOOLCHAIN_IAR/ADuCM3029.icf
@@ -48,7 +48,7 @@ define region ROM_PAGE0_CHECKSUM          = mem:[from MBED_APP_START+ADUCM_VECTO
 define region ROM_REGION                  = mem:[from MBED_APP_START+ADUCM_SECTOR_SIZE size MBED_APP_SIZE-ADUCM_SECTOR_SIZE];
 define region RAM_bank1_region            = mem:[from 0x20000200 size 0x00003E00];
 define region RAM_bank2_region            = mem:[from 0x20004000 size 0x00004000]
-                                          | mem:[from 0x20040000 size 0x00008000];
+                                          | mem:[from 0x20040000 size 0x00007000];
 define block CSTACK   with alignment = 16, size = 0x1000 { };
 define block HEAP     with alignment = 16, size = 0x2000 { };
 do not initialize                         { section .noinit };
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TARGET_EV_COG_AD4050LZ/device/system_ADuCM4050.c
@@ -150,10 +150,10 @@ void SramInit(void)
                                ADI_SRAM_BANK_5 |
                                ADI_SRAM_BANK_6 |
                                ADI_SRAM_BANK_7, true);
-    /* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */
+    /* To disable the instruction SRAM and entire 128K of SRAM is used as DSRAM */
     adi_system_EnableISRAM(false);
-    /* To disable the instruction cache  */
-    adi_system_EnableCache(false);
+    /* To enable the 4K instruction cache out of DSRAM */
+    adi_system_EnableCache(true);
 }
 
 /*!
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_ARM_STD/ADuCM4050.sct
@@ -58,7 +58,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {
 
     RW_IRAM1    0x20040000 EMPTY 0 { }
 
-    ADUCM_IRAM2 0x20000200 0x7E00  { *(+RW) }
+    ADUCM_IRAM2 0x20000200 0x6E00  { *(+RW) }
 
     ADUCM_IRAM3 0x20048000 0x10000 { *(+ZI) }
 
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_GCC_ARM/ADuCM4050.ld
@@ -23,7 +23,7 @@ MEMORY
   /* The rest of the flash */
   FLASH (rx) : ORIGIN = MBED_APP_START + ADUCM_SECTOR_SIZE, LENGTH = MBED_APP_SIZE - ADUCM_SECTOR_SIZE
   /* SRAM bank 0 */
-  DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 32k - 0x200
+  DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 28k - 0x200
   /* SRAM bank 3+4+5+6+7 */
   DSRAM_B (rwx) : ORIGIN = 0x20048000, LENGTH = 64k
   /* stack must not be in bank 1,2,7 where ISRAM or CACHE
diff --git a/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf b/targets/TARGET_Analog_Devices/TARGET_ADUCM4X50/TARGET_ADUCM4050/TOOLCHAIN_IAR/ADuCM4050.icf
@@ -47,7 +47,7 @@ define region ROM_PAGE0_INTVEC            = mem:[from MBED_APP_START size ADUCM_
 define region ROM_PAGE0_CHECKSUM          = mem:[from MBED_APP_START+ADUCM_VECTOR_SIZE size ADUCM_SECTOR_SIZE-ADUCM_VECTOR_SIZE];
 define region ROM_REGION                  = mem:[from MBED_APP_START+ADUCM_SECTOR_SIZE size MBED_APP_SIZE-ADUCM_SECTOR_SIZE];
 define region RAM_bank1_region            = mem:[from 0x20040000 size 0x00008000];
-define region RAM_bank2_region            = mem:[from 0x20000200 size 0x00007E00]
+define region RAM_bank2_region            = mem:[from 0x20000200 size 0x00006E00]
                                           | mem:[from 0x20048000 size 0x00010000];
 define block CSTACK   with alignment = 16, size = 0x2000 { };
 define block HEAP     with alignment = 16, size = 0x6000 { };
diff --git a/targets/targets.json b/targets/targets.json
@@ -644,8 +644,8 @@
         "core": "Cortex-M4F",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "macros": ["__ADUCM4050__", "EV_COG_AD4050LZ"],
-        "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ"],
-        "device_has": ["USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+        "extra_labels": ["Analog_Devices", "ADUCM4X50", "ADUCM4050", "EV_COG_AD4050LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
         "device_name": "ADuCM4050",
         "detect_code": ["0603"],
         "release_versions": ["5"],
@@ -656,8 +656,8 @@
         "core": "Cortex-M3",
         "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
         "macros": ["__ADUCM3029__", "EV_COG_AD3029LZ"],
-        "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ"],
-        "device_has": ["USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
+        "extra_labels": ["Analog_Devices", "ADUCM302X", "ADUCM3029", "EV_COG_AD3029LZ", "FLASH_CMSIS_ALGO"],
+        "device_has": ["FLASH", "USTICKER", "RTC", "SERIAL", "STDIO_MESSAGES", "TRNG", "SLEEP", "INTERRUPTIN", "SPI", "I2C", "ANALOGIN"],
         "device_name": "ADuCM3029",
         "detect_code": ["0602"],
         "release_versions": ["5"],

Original file line number	Diff line number	Diff line change
`@@ -157,8 +157,8 @@ void SramInit(void)`
`157`	`157`	`adi_system_EnableRetention(ADI_SRAM_BANK_2, true);`
`158`	`158`	`/* To disable the instruction SRAM and entire 64K of SRAM is used as DSRAM */`
`159`	`159`	`adi_system_EnableISRAM(false);`
`160`		`- /* To disable the instruction cache */`
`161`		`- adi_system_EnableCache(false);`
	`160`	`+ /* To enable the 4K instruction cache out of DSRAM */`
	`161`	`+ adi_system_EnableCache(true);`
`162`	`162`	`}`
`163`	`163`
`164`	`164`
Original file line number	Diff line number	Diff line change
`@@ -74,7 +74,7 @@ LR_IROM1 MBED_APP_START MBED_APP_SIZE {`
`74`	`74`	`.ANY (+RW +ZI)`
`75`	`75`	`}`
`76`	`76`
`77`		`- ADUCM_IRAM3 0x20040000 0x8000 { ; non-retainable memory region`
	`77`	`+ ADUCM_IRAM3 0x20040000 0x7000 { ; non-retainable memory region`
`78`	`78`	`.ANY (+RW +ZI)`
`79`	`79`	`}`
`80`	`80`	`}`
Original file line number	Diff line number	Diff line change
`@@ -27,7 +27,7 @@ MEMORY`
`27`	`27`	`DSRAM_A (rwx) : ORIGIN = 0x20000200, LENGTH = 16k - 0x200`
`28`	`28`	`DSRAM_C (rwx) : ORIGIN = 0x20004000, LENGTH = 16k`
`29`	`29`	`/* SRAM bank 3 */`
`30`		`- DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 32k`
	`30`	`+ DSRAM_B (rwx) : ORIGIN = 0x20040000, LENGTH = 28k`
`31`	`31`	`}`
`32`	`32`
`33`	`33`	`/* Library configurations */`