[M2351] Change secure/non-secure stack/heap size

ccli8 · ccli8 · commit c3c661da8dac · 2018-07-12T17:52:07.000+08:00
1. Change RTOS-less main stack/RTOS ISR stack size to 2KiB
2. Change secure/non-secure heap size to 16KiB/32KiB for IAR
diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_MICRO/M2351.sct
@@ -21,6 +21,15 @@
  */
 #define NU_TZ_NSC_REGION_BASE       (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
 
+/* Initial/ISR stack size */
+#if (! defined(NU_INITIAL_STACK_SIZE))
+#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#define NU_INITIAL_STACK_SIZE       0x800
+#else
+#define NU_INITIAL_STACK_SIZE       0x800
+#endif
+#endif
+
 #if defined(__DOMAIN_NS) && __DOMAIN_NS
 
 #if (! defined(MBED_APP_START))
@@ -41,12 +50,15 @@ LR_IROM1    MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   0x800
+    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
-    /* Reserve for vectors */
-    ER_IRAMVEC  0x30000800 + NU_TZ_SECURE_SRAM_SIZE         EMPTY   (4*(16 + 102))
+    /* Reserve for vectors
+     *
+     * Vector table base address is required to be 128-byte aligned at a minimum.
+     * A PE might impose further restrictions on it. */
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 102))
     {
     }
 
@@ -84,12 +96,15 @@ LR_IROM1 MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x20000000  EMPTY   0x800
+    ARM_LIB_STACK   0x20000000  EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
-    /* Reserve for vectors */
-    ER_IRAMVEC  0x20000800  EMPTY   (4*(16 + 102))
+    /* Reserve for vectors
+     *
+     * Vector table base address is required to be 128-byte aligned at a minimum.
+     * A PE might impose further restrictions on it. */
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 102))
     {
     }
 
diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_ARM_STD/M2351.sct
@@ -21,6 +21,15 @@
  */
 #define NU_TZ_NSC_REGION_BASE       (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)
 
+/* Initial/ISR stack size */
+#if (! defined(NU_INITIAL_STACK_SIZE))
+#if defined(__DOMAIN_NS) && __DOMAIN_NS
+#define NU_INITIAL_STACK_SIZE       0x800
+#else
+#define NU_INITIAL_STACK_SIZE       0x800
+#endif
+#endif
+
 #if defined(__DOMAIN_NS) && __DOMAIN_NS
 
 #if (! defined(MBED_APP_START))
@@ -41,12 +50,15 @@ LR_IROM1    MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   0x800
+    ARM_LIB_STACK   0x30000000 + NU_TZ_SECURE_SRAM_SIZE     EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
-    /* Reserve for vectors */
-    ER_IRAMVEC  0x30000800 + NU_TZ_SECURE_SRAM_SIZE         EMPTY   (4*(16 + 102))
+    /* Reserve for vectors
+     *
+     * Vector table base address is required to be 128-byte aligned at a minimum.
+     * A PE might impose further restrictions on it. */
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 102))
     {
     }
 
@@ -84,12 +96,15 @@ LR_IROM1 MBED_APP_START
         .ANY (+RO)
     }
 
-    ARM_LIB_STACK   0x20000000  EMPTY   0x800
+    ARM_LIB_STACK   0x20000000  EMPTY   NU_INITIAL_STACK_SIZE
     {
     }
 
-    /* Reserve for vectors */
-    ER_IRAMVEC  0x20000800  EMPTY   (4*(16 + 102))
+    /* Reserve for vectors
+     *
+     * Vector table base address is required to be 128-byte aligned at a minimum.
+     * A PE might impose further restrictions on it. */
+    ER_IRAMVEC  AlignExpr(+0, 128)  EMPTY   (4*(16 + 102))
     {
     }
 
diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_GCC_ARM/M2351.ld
@@ -2,7 +2,11 @@
  * Nuvoton M2351 GCC linker script file
  */
 
+#if defined(__DOMAIN_NS) && __DOMAIN_NS
+StackSize = 0x800;
+#else
 StackSize = 0x800;
+#endif
 
 #include "partition_M2351_sub.h"
 
diff --git a/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf b/targets/TARGET_NUVOTON/TARGET_M2351/device/TOOLCHAIN_IAR/M2351.icf
@@ -25,7 +25,7 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
     
     /*-Sizes-*/
     define symbol __ICFEDIT_size_cstack__           = 0x800;
-    define symbol __ICFEDIT_size_heap__             = 0x4000;
+    define symbol __ICFEDIT_size_heap__             = 0x8000;
 
 } else {
 
@@ -61,8 +61,8 @@ if (isdefinedsymbol(__DOMAIN_NS)) {
     export symbol __NU_TZ_NSC_REGION_SIZE__         = NU_TZ_NSC_REGION_SIZE;
 
     /*-Sizes-*/
-    define symbol __ICFEDIT_size_cstack__ = 0x800;
-    define symbol __ICFEDIT_size_heap__   = 0x1000;
+    define symbol __ICFEDIT_size_cstack__           = 0x800;
+    define symbol __ICFEDIT_size_heap__             = 0x4000;
 }
 
 /**** End of ICF editor section. ###ICF###*/

Original file line number	Diff line number	Diff line change
`@@ -21,6 +21,15 @@`
`21`	`21`	`*/`
`22`	`22`	`#define NU_TZ_NSC_REGION_BASE (MBED_APP_START + MBED_APP_SIZE - 0x2000 - NU_TZ_NSC_REGION_SIZE)`
`23`	`23`
	`24`	`+/* Initial/ISR stack size */`
	`25`	`+#if (! defined(NU_INITIAL_STACK_SIZE))`
	`26`	`+#if defined(__DOMAIN_NS) && __DOMAIN_NS`
	`27`	`+#define NU_INITIAL_STACK_SIZE 0x800`
	`28`	`+#else`
	`29`	`+#define NU_INITIAL_STACK_SIZE 0x800`
	`30`	`+#endif`
	`31`	`+#endif`
	`32`	`+`
`24`	`33`	`#if defined(__DOMAIN_NS) && __DOMAIN_NS`
`25`	`34`
`26`	`35`	`#if (! defined(MBED_APP_START))`
`@@ -41,12 +50,15 @@ LR_IROM1 MBED_APP_START`
`41`	`50`	`.ANY (+RO)`
`42`	`51`	`}`
`43`	`52`
`44`		`- ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY 0x800`
	`53`	`+ ARM_LIB_STACK 0x30000000 + NU_TZ_SECURE_SRAM_SIZE EMPTY NU_INITIAL_STACK_SIZE`
`45`	`54`	`{`
`46`	`55`	`}`
`47`	`56`
`48`		`- /* Reserve for vectors */`
`49`		`- ER_IRAMVEC 0x30000800 + NU_TZ_SECURE_SRAM_SIZE EMPTY (4*(16 + 102))`
	`57`	`+ /* Reserve for vectors`
	`58`	`+ *`
	`59`	`+ * Vector table base address is required to be 128-byte aligned at a minimum.`
	`60`	`+ * A PE might impose further restrictions on it. */`
	`61`	`+ ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))`
`50`	`62`	`{`
`51`	`63`	`}`
`52`	`64`
`@@ -84,12 +96,15 @@ LR_IROM1 MBED_APP_START`
`84`	`96`	`.ANY (+RO)`
`85`	`97`	`}`
`86`	`98`
`87`		`- ARM_LIB_STACK 0x20000000 EMPTY 0x800`
	`99`	`+ ARM_LIB_STACK 0x20000000 EMPTY NU_INITIAL_STACK_SIZE`
`88`	`100`	`{`
`89`	`101`	`}`
`90`	`102`
`91`		`- /* Reserve for vectors */`
`92`		`- ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102))`
	`103`	`+ /* Reserve for vectors`
	`104`	`+ *`
	`105`	`+ * Vector table base address is required to be 128-byte aligned at a minimum.`
	`106`	`+ * A PE might impose further restrictions on it. */`
	`107`	`+ ER_IRAMVEC AlignExpr(+0, 128) EMPTY (4*(16 + 102))`
`93`	`108`	`{`
`94`	`109`	`}`
`95`	`110`