Merge pull request #14149 from jeromecoutant/PR_G4

STM32G4: enable TRNG and correct dual bank flash detection

Author: 0xc0170

targets/TARGET_STM/TARGET_STM32G4/TARGET_STM32G474xE/system_clock.c

@@ -20,22 +20,14 @@
   *                     | 2- USE_PLL_HSE_XTAL (external 8 MHz xtal)
   *                     | 3- USE_PLL_HSI (internal 16 MHz)
   *-----------------------------------------------------------------
-  * SYSCLK(MHz)         | 64
-  * AHBCLK (MHz)        | 64
-  * APB1CLK (MHz)       | 64
+  * SYSCLK(MHz)         | 160 (default configuration) / 170 (CAN disabled)
   * USB capable         | NO
   *-----------------------------------------------------------------
   */
 
 #include "stm32g4xx.h"
 #include "mbed_error.h"
 
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00U /*!< Vector Table base offset field.
-                                   This value must be a multiple of 0x100. */
-
 #define USE_PLL_HSE_EXTC     0x8  // Use external clock (ST Link MCO)
 #define USE_PLL_HSE_XTAL     0x4  // Use external xtal (X3 on board)
 #define USE_PLL_HSI          0x2  // Use HSI internal clock
@@ -90,16 +82,19 @@ void SetSysClock(void)
 /******************************************************************************/
 /*            PLL (clocked by HSE) used as System clock source                */
 /******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+MBED_WEAK uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
 {
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-    /** Configure the main internal regulator output voltage
-    */
+#if HSE_VALUE != 24000000
+#error Unsupported externall clock value, check HSE_VALUE define
+#endif
+
+    /* Configure the main internal regulator output voltage */
+    __HAL_RCC_PWR_CLK_ENABLE();
     HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
-    /** Initializes the CPU, AHB and APB busses clocks
-    */
+
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@@ -116,18 +111,20 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
     RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+#if defined(DEVICE_TRNG)
+    RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+#endif
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         return 0; // FAIL
     }
-    /** Initializes the CPU, AHB and APB busses clocks
-    */
+
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                   | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) {
         return 0; // FAIL
     }
@@ -145,33 +142,41 @@ uint8_t SetSysClock_PLL_HSI(void)
     RCC_OscInitTypeDef RCC_OscInitStruct = {0};
     RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
 
-    /** Configure the main internal regulator output voltage
-    */
-    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
-    /** Initializes the CPU, AHB and APB busses clocks
-    */
+    /* Configure the main internal regulator output voltage */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
+
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
     RCC_OscInitStruct.HSIState = RCC_HSI_ON;
     RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
     RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
     RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
     RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+    //! 170MHz as a core frequency for FDCAN is not suitable for many frequencies,
+    //! as it provides low accuracy. When no FDCAN is used, the full capacity of 170 MHz
+    //! should be standard.
+#if DEVICE_CAN
+    RCC_OscInitStruct.PLL.PLLN = 80;
+#else
     RCC_OscInitStruct.PLL.PLLN = 85;
+#endif
     RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
     RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
     RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
+#if defined(DEVICE_TRNG)
+    RCC_OscInitStruct.OscillatorType |= RCC_OSCILLATORTYPE_HSI48;
+    RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+#endif
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
         return 0; // FAIL
     }
-    /** Initializes the CPU, AHB and APB busses clocks
-    */
+
     RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
                                   | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
     RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
     RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
     RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
-
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_8) != HAL_OK) {
         return 0; // FAIL
     }

targets/TARGET_STM/TARGET_STM32G4/flash_api.c

@@ -48,7 +48,7 @@ static uint32_t GetPage(uint32_t Addr)
 static uint32_t GetBank(uint32_t Addr)
 {
     uint32_t bank = 0;
-#if defined(SYSCFG_MEMRMP_FB_MODE) && defined(FLASH_OPTR_DBANK)
+#if defined (FLASH_OPTR_DBANK)
     if (READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_FB_MODE) == 0) {
         /* No Bank swap */
         if (Addr < (FLASH_BASE + FLASH_BANK_SIZE)) {
@@ -106,7 +106,6 @@ int32_t flash_erase_sector(flash_t *obj, uint32_t address)
     int32_t status = 0;
 
     if ((address >= (FLASH_BASE + FLASH_SIZE)) || (address < FLASH_BASE)) {
-
         return -1;
     }
 

targets/TARGET_STM/trng_api.c

@@ -37,7 +37,7 @@ void trng_init(trng_t *obj)
 {
     uint32_t dummy;
 
-#if defined(RCC_PERIPHCLK_RNG) /* STM32L4 / STM32H7 / STM32WB */
+#if defined(RCC_PERIPHCLK_RNG) /* STM32L4 / STM32H7 / STM32WB / STM32G4 */
 
 #if defined(TARGET_STM32WB)
     /*  No need to configure RngClockSelection as already done in SetSysClock */
@@ -81,6 +81,16 @@ void trng_init(trng_t *obj)
         }
     }
 
+#elif defined(TARGET_STM32G4)
+    /* RNG and USB clocks have the same HSI48 source which has been enabled in SetSysClock */
+    RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
+
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RNG;
+    PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+        error("RNG clock configuration error\n");
+    }
+
 #elif defined(TARGET_STM32L5)
     /*  No need to reconfigure RngClockSelection as alreday done in SetSysClock */
 

targets/targets.json

@@ -2635,6 +2635,7 @@
             "ANALOGOUT",
             "FLASH",
             "MPU",
+            "TRNG",
             "CAN"
         ]
     },