STM32WB RNG: enable use from both M4 and M0+ core

Author: jeromecoutant

targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/hw_conf.h

@@ -28,6 +28,9 @@
  * Semaphores
  * THIS SHALL NO BE CHANGED AS THESE SEMAPHORES ARE USED AS WELL ON THE CM0+
  *****************************************************************************/
+/* Index of the semaphore used to update HSI48 oscillator configuration */
+#define CFG_HW_HSI48_SEMID                                      5
+
 /* Index of the semaphore used to manage the entry Stop Mode procedure */
 #define CFG_HW_ENTRY_STOP_MODE_SEMID                            4
 

targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xx/TARGET_NUCLEO_WB55RG/system_clock.c

@@ -67,13 +67,17 @@ void SetSysClock(void)
 
     __HAL_RCC_HSEM_CLK_ENABLE();
 
+    /* This prevents the CPU2 (M0+) to configure RCC */
     while (LL_HSEM_1StepLock(HSEM, CFG_HW_RCC_SEMID));
 
     Config_HSE();
 
     __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
     __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
 
+    /* This prevents the CPU2 (M0+) to disable the HSI48 oscillator */
+    while (LL_HSEM_1StepLock(HSEM, CFG_HW_HSI48_SEMID));
+
     /* Initializes the CPU, AHB and APB busses clocks */
     RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
     RCC_OscInitStruct.HSEState = RCC_HSE_ON;
@@ -101,8 +105,8 @@ void SetSysClock(void)
         error("HAL_RCC_ClockConfig error\n");
     }
 
-    /** Initializes the peripherals clocks
-    */
+    /* Initializes the peripherals clocks */
+    /* RNG needs to be configured like in M0 core, i.e. with HSI48 */
     PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_USB;
     PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
     PeriphClkInitStruct.RngClockSelection = RCC_RNGCLKSOURCE_HSI48;

targets/TARGET_STM/TARGET_STM32WB/wb_sleep.c

@@ -24,6 +24,7 @@ extern void restore_timer_ctx(void);
 extern int serial_is_tx_ongoing(void);
 extern void PWR_EnterStopMode(void);
 extern void PWR_ExitStopMode(void);
+extern void SetSysClock(void);
 
 
 extern int mbed_sdk_inited;
@@ -58,6 +59,9 @@ void hal_deepsleep(void)
     PWR_EnterStopMode();
     PWR_ExitStopMode();
 
+    /* Force complete clock reconfiguration */
+    SetSysClock();
+
     restore_timer_ctx();
 
     /* us_ticker context restored, allow HAL_GetTick() to read the us_ticker

targets/TARGET_STM/trng_api.c

@@ -25,27 +25,22 @@
 #include "trng_api.h"
 #include "mbed_error.h"
 #include "mbed_atomic.h"
+
 #if defined (TARGET_STM32WB)
 /*  Family specific include for WB with HW semaphores */
 #include "hw.h"
 #include "hw_conf.h"
 #endif
 
-static uint8_t users = 0;
 
 void trng_init(trng_t *obj)
 {
     uint32_t dummy;
 
-    /*  We're only supporting a single user of RNG */
-    if (core_util_atomic_incr_u8(&users, 1) > 1) {
-        error("Only 1 RNG instance supported\r\n");
-    }
-
 #if defined(RCC_PERIPHCLK_RNG) /* STM32L4 / STM32H7 / STM32WB */
 
 #if defined(TARGET_STM32WB)
-    /*  No need to reconfigure RngClockSelection as RNG is already clocked by M0 */
+    /*  No need to configure RngClockSelection as already done in SetSysClock */
 
 #elif defined(TARGET_STM32H7)
     RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
@@ -92,6 +87,7 @@ void trng_init(trng_t *obj)
 #else
 #error("RNG clock not configured");
 #endif
+
 #endif /* defined(RCC_PERIPHCLK_RNG) */
 
     /* RNG Peripheral clock enable */
@@ -109,6 +105,7 @@ void trng_init(trng_t *obj)
     /*  In case RNG is a shared ressource, get the HW semaphore first */
     while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
 #endif
+
     if (HAL_RNG_Init(&obj->handle) != HAL_OK) {
         error("trng_init: HAL_RNG_Init\n");
     }
@@ -123,6 +120,7 @@ void trng_init(trng_t *obj)
 #endif
 }
 
+
 void trng_free(trng_t *obj)
 {
 #if defined(CFG_HW_RNG_SEMID)
@@ -139,10 +137,9 @@ void trng_free(trng_t *obj)
     /* RNG Peripheral clock disable - assume we're the only users of RNG  */
     __HAL_RCC_RNG_CLK_DISABLE();
 #endif
-
-    users = 0;
 }
 
+
 int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
 {
     int ret = 0;
@@ -154,6 +151,11 @@ int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_l
     while (LL_HSEM_1StepLock(HSEM, CFG_HW_RNG_SEMID));
 #endif
 
+#if defined(TARGET_STM32WB)
+    /* M0+ could have disabled RNG */
+    __HAL_RNG_ENABLE(&obj->handle);
+#endif // TARGET_STM32WB
+
     /* Get Random byte */
     while ((*output_length < length) && (ret == 0)) {
         if (HAL_RNG_GenerateRandomNumber(&obj->handle, (uint32_t *)random) != HAL_OK) {