1818 */
1919#include "m480_eth.h"
2020#include "mbed_toolchain.h"
21+ #define NU_TRACE
2122#include "numaker_eth_hal.h"
2223
2324#define ETH_TRIGGER_RX () do{EMAC->RXST = 0;}while(0)
2425#define ETH_TRIGGER_TX () do{EMAC->TXST = 0;}while(0)
2526#define ETH_ENABLE_TX () do{EMAC->CTL |= EMAC_CTL_TXON;}while(0)
26- #define ETH_ENABLE_RX () do{EMAC->CTL |= EMAC_CTL_RXON ;}while(0)
27+ #define ETH_ENABLE_RX () do{EMAC->CTL |= EMAC_CTL_RXON_Msk ;}while(0)
2728#define ETH_DISABLE_TX () do{EMAC->CTL &= ~EMAC_CTL_TXON;}while(0)
28- #define ETH_DISABLE_RX () do{EMAC->CTL &= ~EMAC_CTL_RXON ;}while(0)
29+ #define ETH_DISABLE_RX () do{EMAC->CTL &= ~EMAC_CTL_RXON_Msk ;}while(0)
2930
31+ #define EMAC_ENABLE_INT (emac , u32eIntSel ) ((emac)->INTEN |= (u32eIntSel))
32+ #define EMAC_DISABLE_INT (emac , u32eIntSel ) ((emac)->INTEN &= ~ (u32eIntSel))
3033
3134MBED_ALIGN (4 ) struct eth_descriptor rx_desc [RX_DESCRIPTOR_NUM ];
3235MBED_ALIGN (4 ) struct eth_descriptor tx_desc [TX_DESCRIPTOR_NUM ];
3336
3437struct eth_descriptor volatile * cur_tx_desc_ptr , * cur_rx_desc_ptr , * fin_tx_desc_ptr ;
3538
39+ __attribute__ ((section ("EMAC_RAM" )))
3640MBED_ALIGN (4 ) uint8_t rx_buf [RX_DESCRIPTOR_NUM ][PACKET_BUFFER_SIZE ];
41+ __attribute__ ((section ("EMAC_RAM" )))
3742MBED_ALIGN (4 ) uint8_t tx_buf [TX_DESCRIPTOR_NUM ][PACKET_BUFFER_SIZE ];
3843
3944eth_callback_t nu_eth_txrx_cb = NULL ;
@@ -164,7 +169,7 @@ static void init_rx_desc(void)
164169 rx_desc [i ].status1 = OWNERSHIP_EMAC ;
165170 rx_desc [i ].buf = & rx_buf [i ][0 ];
166171 rx_desc [i ].status2 = 0 ;
167- rx_desc [i ].next = & rx_desc [(i + 1 ) % TX_DESCRIPTOR_NUM ];
172+ rx_desc [i ].next = & rx_desc [(i + 1 ) % RX_DESCRIPTOR_NUM ];
168173 }
169174 EMAC -> RXDSA = (unsigned int )& rx_desc [0 ];
170175 return ;
@@ -263,6 +268,11 @@ void numaker_eth_init(uint8_t *mac_addr)
263268 EMAC_CAMCTL_AMP_Msk |
264269 EMAC_CAMCTL_ABP_Msk ;
265270 EMAC -> CAMEN = 1 ; // Enable CAM entry 0
271+ /* Limit the max receive frame length to 1514 + 4 */
272+ EMAC -> MRFL = 1518 ;
273+
274+ /* Set RX FIFO threshold as 8 words */
275+ EMAC -> FIFOCTL = 0x00200100 ;
266276
267277 /* Limit the max receive frame length to 1514 + 4 */
268278 EMAC -> MRFL = NU_ETH_MAX_FLEN ;
@@ -285,20 +295,22 @@ unsigned int m_status;
285295
286296void EMAC_RX_IRQHandler (void )
287297{
288- // NU_DEBUGF(("%s ... nu_eth_txrx_cb=0x%x\r\n", __FUNCTION__, nu_eth_txrx_cb));
289298 m_status = EMAC -> INTSTS & 0xFFFF ;
290299 EMAC -> INTSTS = m_status ;
291300 if (m_status & EMAC_INTSTS_RXBEIF_Msk ) {
292301 // Shouldn't goes here, unless descriptor corrupted
293- NU_DEBUGF (("RX descriptor corrupted \r\n" ));
294- //return;
302+ mbed_error_printf ("### RX Bus error [0x%x]\r\n" , m_status );
303+ if (nu_eth_txrx_cb != NULL ) nu_eth_txrx_cb ('B' , nu_userData );
304+ return ;
295305 }
306+ EMAC_DISABLE_INT (EMAC , (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk ));
296307 if (nu_eth_txrx_cb != NULL ) nu_eth_txrx_cb ('R' , nu_userData );
297308}
298309
299310
300311void numaker_eth_trigger_rx (void )
301312{
313+ EMAC_ENABLE_INT (EMAC , (EMAC_INTEN_RDUIEN_Msk | EMAC_INTEN_RXGDIEN_Msk ));
302314 ETH_TRIGGER_RX ();
303315}
304316
@@ -317,6 +329,12 @@ int numaker_eth_get_rx_buf(uint16_t *len, uint8_t **buf)
317329 if (status & RXFD_RXGD ) {
318330 * buf = cur_rx_desc_ptr -> buf ;
319331 * len = status & 0xFFFF ;
332+ if ( * len > 1514 ) {
333+ NU_DEBUGF (("%s... unexpected long packet length=%d, buf=0x%x\r\n" , __FUNCTION__ , * len , * buf ));
334+
335+ * len = 0 ; // Skip this unexpected long packet
336+ }
337+ if ( * len == 1514 ) NU_DEBUGF (("%s... length=%d, buf=0x%x\r\n" , __FUNCTION__ , * len , * buf ));
320338 }
321339 return 0 ;
322340}
@@ -335,6 +353,8 @@ void EMAC_TX_IRQHandler(void)
335353 EMAC -> INTSTS = status ;
336354 if (status & EMAC_INTSTS_TXBEIF_Msk ) {
337355 // Shouldn't goes here, unless descriptor corrupted
356+ mbed_error_printf ("### TX Bus error [0x%x]\r\n" , status );
357+ if (nu_eth_txrx_cb != NULL ) nu_eth_txrx_cb ('B' , nu_userData );
338358 return ;
339359 }
340360
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