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[NUCLEO_L152RE] Cleanup in available ports/pins
1 parent bef6fdf commit cbfdc4e

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5 files changed

+26
-141
lines changed

5 files changed

+26
-141
lines changed

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PinNames.h

Lines changed: 0 additions & 67 deletions
Original file line numberDiff line numberDiff line change
@@ -106,77 +106,10 @@ typedef enum {
106106
PC_14 = 0x2E,
107107
PC_15 = 0x2F,
108108

109-
PD_0 = 0x30,
110-
PD_1 = 0x31,
111109
PD_2 = 0x32,
112-
PD_3 = 0x33,
113-
PD_4 = 0x34,
114-
PD_5 = 0x35,
115-
PD_6 = 0x36,
116-
PD_7 = 0x37,
117-
PD_8 = 0x38,
118-
PD_9 = 0x39,
119-
PD_10 = 0x3A,
120-
PD_11 = 0x3B,
121-
PD_12 = 0x3C,
122-
PD_13 = 0x3D,
123-
PD_14 = 0x3E,
124-
PD_15 = 0x3F,
125-
126-
PE_0 = 0x40,
127-
PE_1 = 0x41,
128-
PE_2 = 0x42,
129-
PE_3 = 0x43,
130-
PE_4 = 0x44,
131-
PE_5 = 0x45,
132-
PE_6 = 0x46,
133-
PE_7 = 0x47,
134-
PE_8 = 0x48,
135-
PE_9 = 0x49,
136-
PE_10 = 0x4A,
137-
PE_11 = 0x4B,
138-
PE_12 = 0x4C,
139-
PE_13 = 0x4D,
140-
PE_14 = 0x4E,
141-
PE_15 = 0x4F,
142-
143-
PF_0 = 0x50,
144-
PF_1 = 0x51,
145-
PF_2 = 0x52,
146-
PF_3 = 0x53,
147-
PF_4 = 0x54,
148-
PF_5 = 0x55,
149-
PF_6 = 0x56,
150-
PF_7 = 0x57,
151-
PF_8 = 0x58,
152-
PF_9 = 0x59,
153-
PF_10 = 0x5A,
154-
PF_11 = 0x5B,
155-
PF_12 = 0x5C,
156-
PF_13 = 0x5D,
157-
PF_14 = 0x5E,
158-
PF_15 = 0x5F,
159-
160-
PG_0 = 0x60,
161-
PG_1 = 0x61,
162-
PG_2 = 0x62,
163-
PG_3 = 0x63,
164-
PG_4 = 0x64,
165-
PG_5 = 0x65,
166-
PG_6 = 0x66,
167-
PG_7 = 0x67,
168-
PG_8 = 0x68,
169-
PG_9 = 0x69,
170-
PG_10 = 0x6A,
171-
PG_11 = 0x6B,
172-
PG_12 = 0x6C,
173-
PG_13 = 0x6D,
174-
PG_14 = 0x6E,
175-
PG_15 = 0x6F,
176110

177111
PH_0 = 0x70,
178112
PH_1 = 0x71,
179-
PH_2 = 0x72,
180113

181114
// Arduino connector namings
182115
A0 = PA_0,

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/PortNames.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,9 +39,6 @@ typedef enum {
3939
PortB = 1,
4040
PortC = 2,
4141
PortD = 3,
42-
PortE = 4,
43-
PortF = 5,
44-
PortG = 6,
4542
PortH = 7
4643
} PortName;
4744

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/gpio_api.c

Lines changed: 6 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -44,33 +44,24 @@ void gpio_init(gpio_t *obj, PinName pin, PinDirection direction) {
4444

4545
if (pin == NC) return;
4646

47-
// Get GPIO structure base address
4847
uint32_t pin_number = (uint32_t)pin;
4948
uint32_t port_index = (pin_number >> 4);
5049

50+
// Get GPIO structure base address
5151
switch (port_index) {
52-
case 0:
52+
case PortA:
5353
gpio = (GPIO_TypeDef *)GPIOA_BASE;
5454
break;
55-
case 1:
55+
case PortB:
5656
gpio = (GPIO_TypeDef *)GPIOB_BASE;
5757
break;
58-
case 2:
58+
case PortC:
5959
gpio = (GPIO_TypeDef *)GPIOC_BASE;
6060
break;
61-
case 3:
61+
case PortD:
6262
gpio = (GPIO_TypeDef *)GPIOD_BASE;
6363
break;
64-
case 4:
65-
gpio = (GPIO_TypeDef *)GPIOE_BASE;
66-
break;
67-
case 5:
68-
gpio = (GPIO_TypeDef *)GPIOF_BASE;
69-
break;
70-
case 6:
71-
gpio = (GPIO_TypeDef *)GPIOG_BASE;
72-
break;
73-
case 7:
64+
case PortH:
7465
gpio = (GPIO_TypeDef *)GPIOH_BASE;
7566
break;
7667
default:

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/pinmap.c

Lines changed: 15 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -45,41 +45,29 @@ void pin_function(PinName pin, int data) {
4545
uint32_t pupd = STM_PIN_PUPD(data);
4646
uint32_t afnum = STM_PIN_AFNUM(data);
4747

48-
// Get GPIO structure base address and enable clock
4948
uint32_t pin_number = (uint32_t)pin;
5049
uint32_t pin_index = (pin_number & 0xF);
5150
uint32_t port_index = (pin_number >> 4);
52-
51+
52+
// Get GPIO structure base address and enable clock
5353
switch (port_index) {
54-
case 0:
54+
case PortA:
5555
gpio = (GPIO_TypeDef *)GPIOA_BASE;
5656
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
5757
break;
58-
case 1:
58+
case PortB:
5959
gpio = (GPIO_TypeDef *)GPIOB_BASE;
6060
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
6161
break;
62-
case 2:
62+
case PortC:
6363
gpio = (GPIO_TypeDef *)GPIOC_BASE;
6464
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
6565
break;
66-
case 3:
66+
case PortD:
6767
gpio = (GPIO_TypeDef *)GPIOD_BASE;
6868
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
6969
break;
70-
case 4:
71-
gpio = (GPIO_TypeDef *)GPIOE_BASE;
72-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
73-
break;
74-
case 5:
75-
gpio = (GPIO_TypeDef *)GPIOF_BASE;
76-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
77-
break;
78-
case 6:
79-
gpio = (GPIO_TypeDef *)GPIOG_BASE;
80-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOG, ENABLE);
81-
break;
82-
case 7:
70+
case PortH:
8371
gpio = (GPIO_TypeDef *)GPIOH_BASE;
8472
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOH, ENABLE);
8573
break;
@@ -120,42 +108,30 @@ void pin_mode(PinName pin, PinMode mode) {
120108

121109
if (pin == NC) return;
122110

123-
// Get GPIO structure base address and enable clock
124111
uint32_t pin_number = (uint32_t)pin;
125112
uint32_t port_index = (pin_number >> 4);
126113

114+
// Get GPIO structure base address and enable clock
127115
switch (port_index) {
128-
case 0:
116+
case PortA:
129117
gpio = (GPIO_TypeDef *)GPIOA_BASE;
130118
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
131119
break;
132-
case 1:
120+
case PortB:
133121
gpio = (GPIO_TypeDef *)GPIOB_BASE;
134122
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
135123
break;
136-
case 2:
124+
case PortC:
137125
gpio = (GPIO_TypeDef *)GPIOC_BASE;
138126
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
139127
break;
140-
case 3:
128+
case PortD:
141129
gpio = (GPIO_TypeDef *)GPIOD_BASE;
142-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
143-
break;
144-
case 4:
145-
gpio = (GPIO_TypeDef *)GPIOE_BASE;
146-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
147-
break;
148-
case 5:
149-
gpio = (GPIO_TypeDef *)GPIOF_BASE;
150-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
151-
break;
152-
case 6:
153-
gpio = (GPIO_TypeDef *)GPIOG_BASE;
154-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOG, ENABLE);
130+
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
155131
break;
156-
case 7:
132+
case PortH:
157133
gpio = (GPIO_TypeDef *)GPIOH_BASE;
158-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOH, ENABLE);
134+
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOH, ENABLE);
159135
break;
160136
default:
161137
error("GPIO port number is not correct.");

‎libraries/mbed/targets/hal/TARGET_STM/TARGET_NUCLEO_L152RE/port_api.c

Lines changed: 5 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -47,35 +47,23 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
4747

4848
// Get GPIO structure base address and enable clock
4949
switch (port_index) {
50-
case 0:
50+
case PortA:
5151
gpio = (GPIO_TypeDef *)GPIOA_BASE;
5252
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
5353
break;
54-
case 1:
54+
case PortB:
5555
gpio = (GPIO_TypeDef *)GPIOB_BASE;
5656
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOB, ENABLE);
5757
break;
58-
case 2:
58+
case PortC:
5959
gpio = (GPIO_TypeDef *)GPIOC_BASE;
6060
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOC, ENABLE);
6161
break;
62-
case 3:
62+
case PortD:
6363
gpio = (GPIO_TypeDef *)GPIOD_BASE;
6464
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOD, ENABLE);
6565
break;
66-
case 4:
67-
gpio = (GPIO_TypeDef *)GPIOE_BASE;
68-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOE, ENABLE);
69-
break;
70-
case 5:
71-
gpio = (GPIO_TypeDef *)GPIOF_BASE;
72-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOF, ENABLE);
73-
break;
74-
case 6:
75-
gpio = (GPIO_TypeDef *)GPIOG_BASE;
76-
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOG, ENABLE);
77-
break;
78-
case 7:
66+
case PortH:
7967
gpio = (GPIO_TypeDef *)GPIOH_BASE;
8068
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOH, ENABLE);
8169
break;

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