Merge pull request #5130 from bcostm/freeze_timer_in_debug

theotherjimmy · web-flow · commit cc0b3d05aa91 · 2017-10-02T10:38:57.000-05:00
STM32: Freeze master timer on stop/breakpoint
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/device/hal_tick.h
@@ -47,6 +47,7 @@
 #define TIM_MST_UP_IRQ  TIM1_BRK_UP_TRG_COM_IRQn
 #define TIM_MST_OC_IRQ  TIM1_CC_IRQn
 #define TIM_MST_RCC     __TIM1_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM1()
 
 #define TIM_MST_RESET_ON   __TIM1_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM1_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_BLUEPILL_F103C8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_DISCO_F100RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F1/TARGET_NUCLEO_F103RB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM4
 #define TIM_MST_IRQ  TIM4_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM4_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM4()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM4_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM4_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/hal_tick.h
@@ -46,6 +46,7 @@ extern "C" {
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L011K4/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L031K6/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM21
 #define TIM_MST_IRQ  TIM21_IRQn
 #define TIM_MST_RCC  __TIM21_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM21()
 
 #define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_NZ32_SC151/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L1/TARGET_XDOT_L151CC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L432xC/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/hal_tick.h
@@ -46,6 +46,7 @@
 #define TIM_MST      TIM5
 #define TIM_MST_IRQ  TIM5_IRQn
 #define TIM_MST_RCC  __HAL_RCC_TIM5_CLK_ENABLE()
+#define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM5()
 
 #define TIM_MST_RESET_ON   __HAL_RCC_TIM5_FORCE_RESET()
 #define TIM_MST_RESET_OFF  __HAL_RCC_TIM5_RELEASE_RESET()
diff --git a/targets/TARGET_STM/hal_tick_16b.c b/targets/TARGET_STM/hal_tick_16b.c
@@ -148,12 +148,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
     // Enable timer
     HAL_TIM_Base_Start(&TimMasterHandle);
 
-#ifndef NDEBUG
-#ifdef TIM_MST_DBGMCU_FREEZE
     // Freeze timer on stop/breakpoint
+    // Define the FREEZE_TIMER_ON_DEBUG macro in mbed_app.json for example
+#if !defined(NDEBUG) && defined(FREEZE_TIMER_ON_DEBUG) && defined(TIM_MST_DBGMCU_FREEZE)
     TIM_MST_DBGMCU_FREEZE;
 #endif
-#endif
 
 #if DEBUG_TICK > 0
     __HAL_RCC_GPIOB_CLK_ENABLE();
diff --git a/targets/TARGET_STM/hal_tick_32b.c b/targets/TARGET_STM/hal_tick_32b.c
