Add mapping between SPI defined behavior and test cases

Author: mprse

hal/spi_api.h

@@ -97,40 +97,40 @@ extern "C" {
  * # Defined behavior
  * * ::spi_init initializes the spi_t control structure
  * * ::spi_init configures the pins used by SPI - Verified by ::fpga_spi_test_init_free, ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
- * * ::spi_get_capabilities() fills the given `spi_capabilities_t` instance
- * * ::spi_get_capabilities() should consider the `ssel` pin when evaluation the `support_slave_mode` and `hw_cs_handle` capability
- * * ::spi_get_capabilities(): if the given `ssel` pin cannot be managed by hardware, `support_slave_mode` and `hw_cs_handle` should be false
+ * * ::spi_get_capabilities() fills the given `spi_capabilities_t` instance - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_get_capabilities() should consider the `ssel` pin when evaluation the `support_slave_mode` and `hw_cs_handle` capability - TBD (basic test)
+ * * ::spi_get_capabilities(): if the given `ssel` pin cannot be managed by hardware, `support_slave_mode` and `hw_cs_handle` should be false - TBD (basic test)
  * * At least a symbol width of 8bit must be supported - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
- * * The supported frequency range must include the range [0.2..2] MHz
- * * ::spi_free returns the pins owned by the SPI object to their reset state
- * * ::spi_format sets the number of bits per frame
- * * ::spi_format configures clock polarity and phase
- * * ::spi_format configures master/slave mode
- * * ::spi_frequency sets the SPI baud rate
- * * ::spi_master_write writes a symbol out in master mode and receives a symbol
- * * ::spi_master_block_write writes `tx_length` words to the bus
- * * ::spi_master_block_write reads `rx_length` words from the bus
- * * ::spi_master_block_write returns the maximum of tx_length and rx_length
- * * ::spi_master_block_write specifies the write_fill which is default data transmitted while performing a read
- * * ::spi_get_module returns non-zero if a value is available to read from SPI channel, 0 otherwise
- * * ::spi_slave_read returns a received value out of the SPI receive buffer in slave mode
- * * ::spi_slave_read blocks until a value is available
- * * ::spi_slave_write writes a value to the SPI peripheral in slave mode
- * * ::spi_slave_write blocks until the SPI peripheral can be written to
- * * ::spi_busy returns non-zero if the peripheral is currently transmitting, 0 otherwise
- * * ::spi_master_transfer starts the SPI asynchronous transfer
- * * ::spi_master_transfer writes `tx_len` words to the bus
- * * ::spi_master_transfer reads `rx_len` words from the bus
- * * ::spi_master_transfer specifies the bit width of buffer words
- * * The callback given to ::spi_master_transfer is invoked when the transfer completes (with a success or an error)
- * * ::spi_master_transfer specifies the logical OR of events to be registered
- * * The ::spi_master_transfer function may use the `DMAUsage` hint to select the appropriate async algorithm
- * * ::spi_irq_handler_asynch reads the received values out of the RX FIFO
- * * ::spi_irq_handler_asynch writes values into the TX FIFO
- * * ::spi_irq_handler_asynch checks for transfer termination conditions, such as buffer overflows or transfer complete
- * * ::spi_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise 0
- * * ::spi_abort_asynch aborts an on-going async transfer
- * * ::spi_active returns non-zero if the SPI port is active or zero if it is not
+ * * The supported frequency range must include the range [0.2..2] MHz - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_free returns the pins owned by the SPI object to their reset state - Verified by ::fpga_spi_test_init_free
+ * * ::spi_format sets the number of bits per frame - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_format configures clock polarity and phase - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_format configures master/slave mode - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common; slave mode - TBD
+ * * ::spi_frequency sets the SPI baud rate - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_write writes a symbol out in master mode and receives a symbol - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_block_write writes `tx_length` words to the bus - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_block_write reads `rx_length` words from the bus - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_block_write returns the maximum of tx_length and rx_length - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_block_write specifies the write_fill which is default data transmitted while performing a read - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_get_module returns the SPI module number - TBD (basic test)
+ * * ::spi_slave_read returns a received value out of the SPI receive buffer in slave mode - TBD (SPI slave test)
+ * * ::spi_slave_read blocks until a value is available - TBD (SPI slave test)
+ * * ::spi_slave_write writes a value to the SPI peripheral in slave mode - TBD (SPI slave test)
+ * * ::spi_slave_write blocks until the SPI peripheral can be written to - TBD (SPI slave test)
+ * * ::spi_busy returns non-zero if the peripheral is currently transmitting, 0 otherwise - TBD (basic test)
+ * * ::spi_master_transfer starts the SPI asynchronous transfer - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_transfer writes `tx_len` words to the bus - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_transfer reads `rx_len` words from the bus - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_transfer specifies the bit width of buffer words - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * The callback given to ::spi_master_transfer is invoked when the transfer completes (with a success or an error) - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_master_transfer specifies the logical OR of events to be registered - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * The ::spi_master_transfer function may use the `DMAUsage` hint to select the appropriate async algorithm - Not testable
+ * * ::spi_irq_handler_asynch reads the received values out of the RX FIFO - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_irq_handler_asynch writes values into the TX FIFO - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_irq_handler_asynch checks for transfer termination conditions, such as buffer overflows or transfer complete - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_irq_handler_asynch returns event flags if a transfer termination condition was met, otherwise 0 - Verified by ::fpga_spi_test_common_no_ss and ::fpga_spi_test_common
+ * * ::spi_abort_asynch aborts an on-going async transfer - TBD (basic test)
+ * * ::spi_active returns non-zero if the SPI port is active or zero if it is not - TBD (basic test)
  *
  * # Undefined behavior
  * * Calling ::spi_init multiple times on the same `spi_t` without ::spi_free