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LMESTM
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STM32Cube_FW_F0_V1.7.0
 CMSIS v2.3.0 => v2.3.1 STM32F0 HAL v1.4.0 => v1.5.0 LL Layer introduction for STM32F0
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‎targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f051x8.h

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******************************************************************************
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* @file stm32f051x8.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 27-May-2016
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* @version V2.3.1
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* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F0xx devices.

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/stm32f0xx.h

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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 27-May-2016
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* @version V2.3.1
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* @date 04-November-2016
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* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
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#endif /* USE_HAL_DRIVER */
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/**
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* @brief CMSIS Device version number V2.3.0
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* @brief CMSIS Device version number V2.3.1
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*/
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#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.c

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******************************************************************************
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* @file system_stm32f0xx.c
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* @author MCD Application Team
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* @version V2.3.0
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* @date 27-May-2016
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* @version V2.3.1
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* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/system_stm32f0xx.h

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******************************************************************************
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* @file system_stm32f0xx.h
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* @author MCD Application Team
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* @version V2.3.0
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* @date 27-May-2016
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* @version V2.3.1
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* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
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******************************************************************************
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* @attention

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f030x8.h

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******************************************************************************
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* @file stm32f030x8.h
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
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* @version V2.3.1
6+
* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
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* This file contains all the peripheral register's definitions, bits
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* definitions and memory mapping for STM32F0xx devices.

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/stm32f0xx.h

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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
5+
* @version V2.3.1
6+
* @date 04-November-2016
77
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
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*
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* The file is the unique include file that the application programmer
@@ -112,11 +112,11 @@
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#endif /* USE_HAL_DRIVER */
113113

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/**
115-
* @brief CMSIS Device version number V2.3.0
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* @brief CMSIS Device version number V2.3.1
116116
*/
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#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
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#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.c

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******************************************************************************
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* @file system_stm32f0xx.c
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
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* @version V2.3.1
6+
* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
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*
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* 1. This file provides two functions and one global variable to be called from

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/device/system_stm32f0xx.h

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******************************************************************************
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* @file system_stm32f0xx.h
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
5+
* @version V2.3.1
6+
* @date 04-November-2016
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* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
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******************************************************************************
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* @attention

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f031x6.h

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******************************************************************************
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* @file stm32f031x6.h
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
5+
* @version V2.3.1
6+
* @date 04-November-2016
77
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
88
* This file contains all the peripheral register's definitions, bits
99
* definitions and memory mapping for STM32F0xx devices.

‎targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/stm32f0xx.h

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@@ -2,8 +2,8 @@
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******************************************************************************
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* @file stm32f0xx.h
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* @author MCD Application Team
5-
* @version V2.3.0
6-
* @date 27-May-2016
5+
* @version V2.3.1
6+
* @date 04-November-2016
77
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
88
*
99
* The file is the unique include file that the application programmer
@@ -112,11 +112,11 @@
112112
#endif /* USE_HAL_DRIVER */
113113

114114
/**
115-
* @brief CMSIS Device version number V2.3.0
115+
* @brief CMSIS Device version number V2.3.1
116116
*/
117117
#define __STM32F0_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
118118
#define __STM32F0_DEVICE_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
119-
#define __STM32F0_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
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#define __STM32F0_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __STM32F0_DEVICE_VERSION ((__STM32F0_DEVICE_VERSION_MAIN << 24)\
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|(__STM32F0_DEVICE_VERSION_SUB1 << 16)\

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